diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-14 20:39:18 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-14 20:39:18 +0100 |
| commit | 26ac1ea5590c2710d050bfe2630c1546f109d28c (patch) | |
| tree | ed99be4a6ca155c60d687575b6789e9b78f51293 /target-sh4 | |
| parent | 442599a340ad04f2915c471430ae8a93cb42b261 (diff) | |
target-sh4: define FPSCR constants
Define FPSCR constants for all field and use them instead of hardcoded
values.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4')
| -rw-r--r-- | target-sh4/cpu.h | 35 | ||||
| -rw-r--r-- | target-sh4/op_helper.c | 7 | ||||
| -rw-r--r-- | target-sh4/translate.c | 4 |
3 files changed, 37 insertions, 9 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 8ccf25cafb..fe33b8afc0 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -61,10 +61,37 @@ #define SR_S (1 << 1) #define SR_T (1 << 0) -#define FPSCR_FR (1 << 21) -#define FPSCR_SZ (1 << 20) -#define FPSCR_PR (1 << 19) -#define FPSCR_DN (1 << 18) +#define FPSCR_MASK (0x003fffff) +#define FPSCR_FR (1 << 21) +#define FPSCR_SZ (1 << 20) +#define FPSCR_PR (1 << 19) +#define FPSCR_DN (1 << 18) +#define FPSCR_CAUSE_MASK (0x3f << 12) +#define FPSCR_CAUSE_SHIFT (12) +#define FPSCR_CAUSE_E (1 << 17) +#define FPSCR_CAUSE_V (1 << 16) +#define FPSCR_CAUSE_Z (1 << 15) +#define FPSCR_CAUSE_O (1 << 14) +#define FPSCR_CAUSE_U (1 << 13) +#define FPSCR_CAUSE_I (1 << 12) +#define FPSCR_ENABLE_MASK (0x1f << 7) +#define FPSCR_ENABLE_SHIFT (7) +#define FPSCR_ENABLE_V (1 << 11) +#define FPSCR_ENABLE_Z (1 << 10) +#define FPSCR_ENABLE_O (1 << 9) +#define FPSCR_ENABLE_U (1 << 8) +#define FPSCR_ENABLE_I (1 << 7) +#define FPSCR_FLAG_MASK (0x1f << 2) +#define FPSCR_FLAG_SHIFT (2) +#define FPSCR_FLAG_V (1 << 6) +#define FPSCR_FLAG_Z (1 << 5) +#define FPSCR_FLAG_O (1 << 4) +#define FPSCR_FLAG_U (1 << 3) +#define FPSCR_FLAG_I (1 << 2) +#define FPSCR_RM_MASK (0x03 << 0) +#define FPSCR_RM_NEAREST (0 << 0) +#define FPSCR_RM_ZERO (1 << 0) + #define DELAY_SLOT (1 << 0) #define DELAY_SLOT_CONDITIONAL (1 << 1) #define DELAY_SLOT_TRUE (1 << 2) diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 2e5f5552a2..d69b94b0b1 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -443,11 +443,12 @@ static inline void clr_t(void) void helper_ld_fpscr(uint32_t val) { - env->fpscr = val & 0x003fffff; - if (val & 0x01) + env->fpscr = val & FPSCR_MASK; + if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) { set_float_rounding_mode(float_round_to_zero, &env->fp_status); - else + } else { set_float_rounding_mode(float_round_nearest_even, &env->fp_status); + } } uint32_t helper_fabs_FT(uint32_t t0) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 1858423ff7..d4cd0a3f86 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -203,10 +203,10 @@ static void cpu_sh4_reset(CPUSH4State * env) env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ #else - env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ + env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ set_float_rounding_mode(float_round_to_zero, &env->fp_status); #endif - set_default_nan_mode(1, &env->vfp.fp_status); + set_default_nan_mode(1, &env->fp_status); env->mmucr = 0; } |