diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-07-02 15:20:06 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-07-02 15:20:06 +0000 |
| commit | 9d1d106a3d95ada648703e871975897c1cf05383 (patch) | |
| tree | 9ba5e29aaf07a9c09c5f3247d7de39621d130927 /target-mips | |
| parent | ae022501f2a17f522b33db2af54ab42d7f456ce8 (diff) | |
unaligned load fix (Ralf Baechle)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1471 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index cb1791f099..386bf74b3f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -329,6 +329,7 @@ static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt, opn = "lbu"; break; case OPC_LWL: + GEN_LOAD_REG_TN(T1, rt); op_ldst(lwl); GEN_STORE_TN_REG(rt, T0); opn = "lwl"; @@ -339,6 +340,7 @@ static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt, opn = "swr"; break; case OPC_LWR: + GEN_LOAD_REG_TN(T1, rt); op_ldst(lwr); GEN_STORE_TN_REG(rt, T0); opn = "lwr"; |