diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-21 21:06:42 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-11-21 21:06:42 +0000 |
| commit | 96e2fc41a94f190994dfb56d47d609a658bfe67c (patch) | |
| tree | 07bb16d585c39d29d4006830ebc2b5a3e7e0133d /hw/sh_timer.c | |
| parent | 380ce5ba932724aa2bb2b8564ee4cc47cea15570 (diff) | |
SH4: Use qemu_irq in timer emulation.
* hw/sh.h (tmu012_init): Accept qemu_irq, not intc_source.
* hw/sh7750.c (sh7750_init): Pass qemu_irq to tmu012_init.
* hw/sh_intc.c (sh_intc_set_irq): New.
(sh_intc_init): Allocate irqs.
* hw/sh_intc.h (struct intc_desc): New field irqs.
* hw/sh_timer.c (sh_timer_state): Use qemu_irq, not intc_source.
(sh_timer_update): Use qemu_set_irq, not sh_intc_toggle_source.
(sh_timer_init, tmu012_init): Adjust.
(Vladimir Prus)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5768 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/sh_timer.c')
| -rw-r--r-- | hw/sh_timer.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/hw/sh_timer.c b/hw/sh_timer.c index df265d2d2a..743a970a4b 100644 --- a/hw/sh_timer.c +++ b/hw/sh_timer.c @@ -36,7 +36,7 @@ typedef struct { int old_level; int feat; int enabled; - struct intc_source *irq; + qemu_irq irq; } sh_timer_state; /* Check all active timers, and schedule the next timer interrupt. */ @@ -46,7 +46,7 @@ static void sh_timer_update(sh_timer_state *s) int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); if (new_level != s->old_level) - sh_intc_toggle_source(s->irq, 0, new_level ? 1 : -1); + qemu_set_irq (s->irq, new_level); s->old_level = s->int_level; s->int_level = new_level; @@ -185,7 +185,7 @@ static void sh_timer_tick(void *opaque) sh_timer_update(s); } -static void *sh_timer_init(uint32_t freq, int feat, struct intc_source *irq) +static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) { sh_timer_state *s; QEMUBH *bh; @@ -307,8 +307,8 @@ static CPUWriteMemoryFunc *tmu012_writefn[] = { }; void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, - struct intc_source *ch0_irq, struct intc_source *ch1_irq, - struct intc_source *ch2_irq0, struct intc_source *ch2_irq1) + qemu_irq ch0_irq, qemu_irq ch1_irq, + qemu_irq ch2_irq0, qemu_irq ch2_irq1) { int iomemtype; tmu012_state *s; |