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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-10 15:02:07 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-10 15:02:07 +0000
commit4efbe58fb57314f422578a543fe3f47ffc854b68 (patch)
treeec0c5e97bb9298cddba5fa4b5a69e58dd1d33a86 /hw/pckbd.c
parentf65ed4c1529f29a7d62d6733eaa50bed24a4b2ed (diff)
MIPS Magnum: fix memory-mapped i8042
Current implementation of memory-mapped i8042 controller is atm implemented with an interface shift (it_shift) parameter, like most all memory-mapped devices in Qemu. However, this isn't suitable for MIPS Magnum, where i8042 controller is at 0x80005000 up to 0x80005fff. Thomas Bogendoerfer (from #mipslinux) tested the behaviour of a real machine, and found that odd addresses are for status/command register, and even addresses for data register. Attached patch implements this behaviour by replacing the it_shift parameter by a mask one. Incidentally, keyboard now works on OpenBSD 2.3, which accesses i8042 controller at 0x80005060 and 0x80005061. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5962 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pckbd.c')
-rw-r--r--hw/pckbd.c29
1 files changed, 11 insertions, 18 deletions
diff --git a/hw/pckbd.c b/hw/pckbd.c
index cceea4a5d1..3a004f7a8e 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -125,7 +125,7 @@ typedef struct KBDState {
qemu_irq irq_kbd;
qemu_irq irq_mouse;
- int it_shift;
+ target_phys_addr_t mask;
} KBDState;
static KBDState kbd_state;
@@ -391,28 +391,20 @@ static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
{
KBDState *s = opaque;
- switch (addr >> s->it_shift) {
- case 0:
- return kbd_read_data(s, 0) & 0xff;
- case 1:
+ if (addr & s->mask)
return kbd_read_status(s, 0) & 0xff;
- default:
- return 0xff;
- }
+ else
+ return kbd_read_data(s, 0) & 0xff;
}
static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
KBDState *s = opaque;
- switch (addr >> s->it_shift) {
- case 0:
- kbd_write_data(s, 0, value & 0xff);
- break;
- case 1:
+ if (addr & s->mask)
kbd_write_command(s, 0, value & 0xff);
- break;
- }
+ else
+ kbd_write_data(s, 0, value & 0xff);
}
static CPUReadMemoryFunc *kbd_mm_read[] = {
@@ -428,19 +420,20 @@ static CPUWriteMemoryFunc *kbd_mm_write[] = {
};
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, int it_shift)
+ target_phys_addr_t base, ram_addr_t size,
+ target_phys_addr_t mask)
{
KBDState *s = &kbd_state;
int s_io_memory;
s->irq_kbd = kbd_irq;
s->irq_mouse = mouse_irq;
- s->it_shift = it_shift;
+ s->mask = mask;
kbd_reset(s);
register_savevm("pckbd", 0, 3, kbd_save, kbd_load, s);
s_io_memory = cpu_register_io_memory(0, kbd_mm_read, kbd_mm_write, s);
- cpu_register_physical_memory(base, 2 << it_shift, s_io_memory);
+ cpu_register_physical_memory(base, size, s_io_memory);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);