diff options
| author | Alistair Francis <alistair.francis@xilinx.com> | 2015-06-18 21:16:42 -0700 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2015-06-21 17:20:16 +1000 |
| commit | 6fad9e986b82c7c7ed7cfa0cc3ee38b3510a5432 (patch) | |
| tree | 92fbcfa74647cb4a7da90c95047da734ffb171f9 | |
| parent | 72e38754853443830152a3cfe586db1d9b15e8fe (diff) | |
target-microblaze: Convert pvr-full to a CPU property
Originally the pvr-full PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| -rw-r--r-- | target-microblaze/cpu-qom.h | 1 | ||||
| -rw-r--r-- | target-microblaze/cpu.c | 7 | ||||
| -rw-r--r-- | target-microblaze/cpu.h | 4 | ||||
| -rw-r--r-- | target-microblaze/helper.c | 4 |
4 files changed, 10 insertions, 6 deletions
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index 7da25fa80e..34f6273ad1 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU { bool dcache_writeback; bool endi; char *version; + uint8_t pvr; } cfg; CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index df3dd891a4..ac390ce732 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -130,8 +130,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) qemu_init_vcpu(cs); - env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ - | PVR0_USE_BARREL_MASK \ + env->pvr.regs[0] = PVR0_USE_BARREL_MASK \ | PVR0_USE_DIV_MASK \ | PVR0_USE_HW_MUL_MASK \ | PVR0_USE_EXC_MASK \ @@ -166,7 +165,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | - (version_code << 16); + (version_code << 16) | + (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0); @@ -228,6 +228,7 @@ static Property mb_properties[] = { false), DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), + DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 0f82abd304..0dd164ff15 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -212,7 +212,9 @@ typedef struct CPUMBState CPUMBState; /* MSR Reset value PVR mask */ #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF - +#define C_PVR_NONE 0 +#define C_PVR_BASIC 1 +#define C_PVR_FULL 2 /* CPU flags. */ diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 5156c12dc6..8257b0e0f2 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, mmu_available = 0; if (cpu->cfg.use_mmu) { mmu_available = 1; - if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK) - && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) { + if ((cpu->cfg.pvr == C_PVR_FULL) && + (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) { mmu_available = 0; } } |