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2018-01-12broadcom/vc5: Add a test for .ifb in ADD ops.Eric Anholt1-0/+1
2018-01-12broadcom/vc5: Add the new tesselation opcodes in V3D 4.1.Eric Anholt2-1/+5
2018-01-12broadcom/vc5: Use a physical-reg-only register class for LDVPM.Eric Anholt2-8/+21
2018-01-12broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.Eric Anholt9-51/+197
2018-01-12broadcom/vc5: Drop dead VC5_QPU_* defines from qpu_instr.c.Eric Anholt1-80/+0
2018-01-12broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates.Eric Anholt4-1/+94
2018-01-12broadcom/vc5: Enable the driver on V3D 4.1Eric Anholt1-1/+1
2018-01-12broadcom/vc5: Port the simulator to support V3D 4.1Eric Anholt9-125/+216
2018-01-12broadcom/vc5: Drop signal bit #defines.Eric Anholt2-8/+0
2018-01-12broadcom/vc5: Add support for V3Dv4 signal bits.Eric Anholt12-45/+322
2018-01-12broadcom/vc5: Fix pack/unpack of vfmul input unpack flags.Eric Anholt2-0/+40
2018-01-12broadcom/vc5: Port the RCL setup to V3D4.1.Eric Anholt7-58/+360
2018-01-12broadcom/vc5: Fix per-tile extra clear packet.Eric Anholt1-1/+1
2018-01-12broadcom/vc5: Move the TLB loads and stores to helper functions.Eric Anholt1-35/+50
2018-01-12broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.Eric Anholt7-10/+24
2018-01-12broadcom/vc5: Introduce v3dx_macros.h and v3dx_pack.h headers.Eric Anholt3-1/+88
2018-01-12broadcom/cle: Fix error path of missing a "type" in the XML.Eric Anholt1-1/+2
2018-01-12broadcom/vc5: Add XML for V3D v4.1 (BCM7278)Eric Anholt3-1/+1054
2018-01-12ac: add 'const' qualifiers to the shader info passSamuel Pitoiset2-8/+11
2018-01-12ac: remove unused ac_nir_compiler_options from gather_info_input_decl()Samuel Pitoiset1-4/+2
2018-01-12nir: add a 'const' qualifier to nir_ssa_def_components_read()Samuel Pitoiset2-2/+2
2018-01-12loader/dri3: Avoid freeing renderbuffers in useThomas Hellstrom1-3/+3
2018-01-12anv: VkDescriptorSetLayoutBinding can have descriptorCount == 0Samuel Iglesias Gonsálvez1-1/+3
2018-01-12mesa: require at least 14 UBOs for GL 4.3Roland Scheidegger1-0/+1
2018-01-12util: fix NORETURN for msvc, add HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.hRoland Scheidegger2-4/+9
2018-01-12radv: don't emit unneeded vertex state.Dave Airlie2-8/+49
2018-01-12radv: trim buffer load result (fixes dota2)Dave Airlie1-1/+1
2018-01-11meson: add variable for including include/GL/internalDylan Baker3-10/+5
2018-01-11meson: define inc_gbm as empty if not otherwise assignedDylan Baker1-0/+2
2018-01-11meson: move libsensors dependency to libgalliumDylan Baker8-13/+7
2018-01-11meson: Use dependencies for nirDylan Baker18-50/+72
2018-01-11meson: don't use intermediate variables that are immediately discardedDylan Baker5-14/+7
2018-01-11meson: Use consistent style for testsDylan Baker20-151/+199
2018-01-11meson: Use include variablesDylan Baker1-1/+1
2018-01-11meson: Use consistent styleDylan Baker17-85/+148
2018-01-11i965: Use UD types for gl_SampleID setupJason Ekstrand1-3/+3
2018-01-11i965/fs: Use UW types when using V immediatesJason Ekstrand2-5/+5
2018-01-12ac/nir: fix translation of nir_op_fsign for doublesTimothy Arceri1-7/+19
2018-01-12ac: add f64_0 to the llvm build contextTimothy Arceri2-0/+2
2018-01-12ac/nir: fix translation of nir_op_frcp for doublesTimothy Arceri1-1/+2
2018-01-12ac/nir: fix translation of nir_op_frsq for doublesTimothy Arceri1-1/+2
2018-01-12ac: add f64_1 to the llvm build contextTimothy Arceri2-0/+2
2018-01-11radv: reset semaphores & fences on sync_file export.Bas Nieuwenhuizen1-0/+16
2018-01-11intel: Add more Coffee Lake PCI IDsAnuj Phogat1-1/+9
2018-01-11Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""Matt Turner1-4/+8
2018-01-11i965/fs: Add/use functions to convert to 3src_align1 vstride/hstrideMatt Turner1-28/+41
2018-01-11anv: Make sure state on primary is correct after CmdExecuteCommandsAlex Smith1-0/+9
2018-01-11svga: simplify failure code in emit_rss_vgpu9()Brian Paul1-17/+12
2018-01-11svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()Brian Paul1-57/+57
2018-01-11svga: add assertion in svga_queue_rs()Brian Paul1-0/+1
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