broadcom/vc5: Port the simulator to support V3D 4.1

This required moving the register accesses to a separate v3dx file, since
the register definitions for each V3D version collide.  It seems that
initializing the v3d_hw from a file dictating 3.3
(v3d_simulator_wrapper.cpp) is safe, though.

9 files changed, 216 insertions, 125 deletions

diff --git a/src/gallium/drivers/vc5/Makefile.sources b/src/gallium/drivers/vc5/Makefile.sources
index f942c74ca3..8377af77fb 100644
--- a/src/gallium/drivers/vc5/Makefile.sources
+++ b/src/gallium/drivers/vc5/Makefile.sources
@@ -26,5 +26,6 @@ C_SOURCES := \
 	$()
 
 VC5_PER_VERSION_SOURCES = \
+	v3dx_simulator.c \
 	vc5_rcl.c \
 	$()
diff --git a/src/gallium/drivers/vc5/meson.build b/src/gallium/drivers/vc5/meson.build
index ad4395212b..951c321b51 100644
--- a/src/gallium/drivers/vc5/meson.build
+++ b/src/gallium/drivers/vc5/meson.build
@@ -46,6 +46,7 @@ files_libvc5 = files(
 )
 
 files_per_version = files(
+  'v3dx_simulator.c',
   'vc5_rcl.c',
 )
 
diff --git a/src/gallium/drivers/vc5/v3dx_context.h b/src/gallium/drivers/vc5/v3dx_context.h
index 19ca956922..e6bbfc6b3f 100644
--- a/src/gallium/drivers/vc5/v3dx_context.h
+++ b/src/gallium/drivers/vc5/v3dx_context.h
@@ -26,4 +26,12 @@
  * be included from vc5_context.h.
  */
 
+struct v3d_hw;
+
 void v3dX(emit_rcl)(struct vc5_job *job);
+
+void v3dX(simulator_init_regs)(struct v3d_hw *v3d);
+int v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
+                                    struct drm_vc5_get_param *args);
+void v3dX(simulator_flush)(struct v3d_hw *v3d, struct drm_vc5_submit_cl *submit,
+                           uint32_t gmp_ofs);
diff --git a/src/gallium/drivers/vc5/v3dx_simulator.c b/src/gallium/drivers/vc5/v3dx_simulator.c
new file mode 100644
index 0000000000..2180787891
--- /dev/null
+++ b/src/gallium/drivers/vc5/v3dx_simulator.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright © 2014-2017 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/**
+ * @file vc5_simulator_hw.c
+ *
+ * Implements the actual HW interaction betweeh the GL driver's VC5 simulator and the simulator.
+ *
+ * The register headers between V3D versions will have conflicting defines, so
+ * all register interactions appear in this file and are compiled per V3D version
+ * we support.
+ */
+
+#ifdef USE_VC5_SIMULATOR
+
+#include "vc5_screen.h"
+#include "vc5_context.h"
+#include "vc5_simulator_wrapper.h"
+
+#define HW_REGISTER_RO(x) (x)
+#define HW_REGISTER_RW(x) (x)
+#if V3D_VERSION >= 41
+#include "libs/core/v3d/registers/4.1.34.0/v3d.h"
+#else
+#include "libs/core/v3d/registers/3.3.0.0/v3d.h"
+#endif
+
+#define V3D_WRITE(reg, val) v3d_hw_write_reg(v3d, reg, val)
+#define V3D_READ(reg) v3d_hw_read_reg(v3d, reg)
+
+static void
+vc5_flush_l3(struct v3d_hw *v3d)
+{
+        if (!v3d_hw_has_gca(v3d))
+                return;
+
+#if V3D_VERSION < 40
+        uint32_t gca_ctrl = V3D_READ(V3D_GCA_CACHE_CTRL);
+
+        V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH_SET);
+        V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH_SET);
+#endif
+}
+
+/* Invalidates the L2 cache.  This is a read-only cache. */
+static void
+vc5_flush_l2(struct v3d_hw *v3d)
+{
+        V3D_WRITE(V3D_CTL_0_L2CACTL,
+                  V3D_CTL_0_L2CACTL_L2CCLR_SET |
+                  V3D_CTL_0_L2CACTL_L2CENA_SET);
+}
+
+/* Invalidates texture L2 cachelines */
+static void
+vc5_flush_l2t(struct v3d_hw *v3d)
+{
+        V3D_WRITE(V3D_CTL_0_L2TFLSTA, 0);
+        V3D_WRITE(V3D_CTL_0_L2TFLEND, ~0);
+        V3D_WRITE(V3D_CTL_0_L2TCACTL,
+                  V3D_CTL_0_L2TCACTL_L2TFLS_SET |
+                  (0 << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
+}
+
+/* Invalidates the slice caches.  These are read-only caches. */
+static void
+vc5_flush_slices(struct v3d_hw *v3d)
+{
+        V3D_WRITE(V3D_CTL_0_SLCACTL, ~0);
+}
+
+static void
+vc5_flush_caches(struct v3d_hw *v3d)
+{
+        vc5_flush_l3(v3d);
+        vc5_flush_l2(v3d);
+        vc5_flush_l2t(v3d);
+        vc5_flush_slices(v3d);
+}
+
+int
+v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
+                                struct drm_vc5_get_param *args)
+{
+        static const uint32_t reg_map[] = {
+                [DRM_VC5_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG,
+                [DRM_VC5_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1,
+                [DRM_VC5_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2,
+                [DRM_VC5_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3,
+                [DRM_VC5_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_0_IDENT0,
+                [DRM_VC5_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_0_IDENT1,
+                [DRM_VC5_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_0_IDENT2,
+        };
+
+        if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) {
+                args->value = V3D_READ(reg_map[args->param]);
+                return 0;
+        }
+
+        fprintf(stderr, "Unknown DRM_IOCTL_VC5_GET_PARAM(%lld)\n",
+                (long long)args->value);
+        abort();
+}
+
+void
+v3dX(simulator_init_regs)(struct v3d_hw *v3d)
+{
+#if V3D_VERSION == 33
+        /* Set OVRTMUOUT to match kernel behavior.
+         *
+         * This means that the texture sampler uniform configuration's tmu
+         * output type field is used, instead of using the hardware default
+         * behavior based on the texture type.  If you want the default
+         * behavior, you can still put "2" in the indirect texture state's
+         * output_type field.
+         */
+        V3D_WRITE(V3D_CTL_0_MISCCFG, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET);
+#endif
+}
+
+void
+v3dX(simulator_flush)(struct v3d_hw *v3d, struct drm_vc5_submit_cl *submit,
+                      uint32_t gmp_ofs)
+{
+        /* Completely reset the GMP. */
+        V3D_WRITE(V3D_GMP_0_CFG,
+                  V3D_GMP_0_CFG_PROTENABLE_SET);
+        V3D_WRITE(V3D_GMP_0_TABLE_ADDR, gmp_ofs);
+        V3D_WRITE(V3D_GMP_0_CLEAR_LOAD, ~0);
+        while (V3D_READ(V3D_GMP_0_STATUS) &
+               V3D_GMP_0_STATUS_CFG_BUSY_SET) {
+                ;
+        }
+
+        vc5_flush_caches(v3d);
+
+        V3D_WRITE(V3D_CLE_0_CT0QBA, submit->bcl_start);
+        V3D_WRITE(V3D_CLE_0_CT0QEA, submit->bcl_end);
+
+        /* Wait for bin to complete before firing render, as it seems the
+         * simulator doesn't implement the semaphores.
+         */
+        while (V3D_READ(V3D_CLE_0_CT0CA) !=
+               V3D_READ(V3D_CLE_0_CT0EA)) {
+                v3d_hw_tick(v3d);
+        }
+
+        V3D_WRITE(V3D_CLE_0_CT1QBA, submit->rcl_start);
+        V3D_WRITE(V3D_CLE_0_CT1QEA, submit->rcl_end);
+
+        while (V3D_READ(V3D_CLE_0_CT1CA) !=
+               V3D_READ(V3D_CLE_0_CT1EA) ||
+               V3D_READ(V3D_CLE_1_CT1CA) !=
+               V3D_READ(V3D_CLE_1_CT1EA)) {
+                v3d_hw_tick(v3d);
+        }
+}
+
+#endif /* USE_VC5_SIMULATOR */
diff --git a/src/gallium/drivers/vc5/vc5_context.h b/src/gallium/drivers/vc5/vc5_context.h
index 0e7cff7482..70ee333c43 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -452,8 +452,6 @@ void vc5_program_fini(struct pipe_context *pctx);
 void vc5_query_init(struct pipe_context *pctx);
 
 void vc5_simulator_init(struct vc5_screen *screen);
-void vc5_simulator_init(struct vc5_screen *screen);
-void vc5_simulator_destroy(struct vc5_screen *screen);
 void vc5_simulator_destroy(struct vc5_screen *screen);
 int vc5_simulator_flush(struct vc5_context *vc5,
                         struct drm_vc5_submit_cl *args,
diff --git a/src/gallium/drivers/vc5/vc5_job.c b/src/gallium/drivers/vc5/vc5_job.c
index 02a7d53a99..a5edbe7c20 100644
--- a/src/gallium/drivers/vc5/vc5_job.c
+++ b/src/gallium/drivers/vc5/vc5_job.c
@@ -371,6 +371,8 @@ vc5_clif_dump(struct vc5_context *vc5, struct vc5_job *job)
 void
 vc5_job_submit(struct vc5_context *vc5, struct vc5_job *job)
 {
+        MAYBE_UNUSED struct vc5_screen *screen = vc5->screen;
+
         if (!job->needs_flush)
                 goto done;
 
diff --git a/src/gallium/drivers/vc5/vc5_simulator.c b/src/gallium/drivers/vc5/vc5_simulator.c
index 95aa79d0a0..d3ab2bc539 100644
--- a/src/gallium/drivers/vc5/vc5_simulator.c
+++ b/src/gallium/drivers/vc5/vc5_simulator.c
@@ -56,10 +56,6 @@
 #include "util/u_mm.h"
 #include "vc5_simulator_wrapper.h"
 
-#define HW_REGISTER_RO(x) (x)
-#define HW_REGISTER_RW(x) (x)
-#include "libs/core/v3d/registers/3.3.0.0/v3d.h"
-
 #include "vc5_screen.h"
 #include "vc5_context.h"
 
@@ -68,6 +64,7 @@ static struct vc5_simulator_state {
         mtx_t mutex;
 
         struct v3d_hw *v3d;
+        int ver;
 
         /* Base virtual address of the heap. */
         void *mem;
@@ -359,57 +356,6 @@ vc5_dump_to_file(struct vc5_exec_info *exec)
 }
 #endif
 
-#define V3D_WRITE(reg, val) v3d_hw_write_reg(sim_state.v3d, reg, val)
-#define V3D_READ(reg) v3d_hw_read_reg(sim_state.v3d, reg)
-
-static void
-vc5_flush_l3(void)
-{
-        if (!v3d_hw_has_gca(sim_state.v3d))
-                return;
-
-        uint32_t gca_ctrl = V3D_READ(V3D_GCA_CACHE_CTRL);
-
-        V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH_SET);
-        V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH_SET);
-}
-
-/* Invalidates the L2 cache.  This is a read-only cache. */
-static void
-vc5_flush_l2(void)
-{
-        V3D_WRITE(V3D_CTL_0_L2CACTL,
-                  V3D_CTL_0_L2CACTL_L2CCLR_SET |
-                  V3D_CTL_0_L2CACTL_L2CENA_SET);
-}
-
-/* Invalidates texture L2 cachelines */
-static void
-vc5_flush_l2t(void)
-{
-        V3D_WRITE(V3D_CTL_0_L2TFLSTA, 0);
-        V3D_WRITE(V3D_CTL_0_L2TFLEND, ~0);
-        V3D_WRITE(V3D_CTL_0_L2TCACTL,
-                  V3D_CTL_0_L2TCACTL_L2TFLS_SET |
-                  (0 << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
-}
-
-/* Invalidates the slice caches.  These are read-only caches. */
-static void
-vc5_flush_slices(void)
-{
-        V3D_WRITE(V3D_CTL_0_SLCACTL, ~0);
-}
-
-static void
-vc5_flush_caches(void)
-{
-        vc5_flush_l3();
-        vc5_flush_l2();
-        vc5_flush_l2t();
-        vc5_flush_slices();
-}
-
 int
 vc5_simulator_flush(struct vc5_context *vc5,
                     struct drm_vc5_submit_cl *submit, struct vc5_job *job)
@@ -447,38 +393,10 @@ vc5_simulator_flush(struct vc5_context *vc5,
 
         //vc5_dump_to_file(&exec);
 
-        /* Completely reset the GMP. */
-        v3d_hw_write_reg(sim_state.v3d, V3D_GMP_0_CFG,
-                         V3D_GMP_0_CFG_PROTENABLE_SET);
-        v3d_hw_write_reg(sim_state.v3d, V3D_GMP_0_TABLE_ADDR, file->gmp->ofs);
-        v3d_hw_write_reg(sim_state.v3d, V3D_GMP_0_CLEAR_LOAD, ~0);
-        while (v3d_hw_read_reg(sim_state.v3d, V3D_GMP_0_STATUS) &
-               V3D_GMP_0_STATUS_CFG_BUSY_SET) {
-                ;
-        }
-
-        vc5_flush_caches();
-
-        v3d_hw_write_reg(sim_state.v3d, V3D_CLE_0_CT0QBA, submit->bcl_start);
-        v3d_hw_write_reg(sim_state.v3d, V3D_CLE_0_CT0QEA, submit->bcl_end);
-
-        /* Wait for bin to complete before firing render, as it seems the
-         * simulator doesn't implement the semaphores.
-         */
-        while (v3d_hw_read_reg(sim_state.v3d, V3D_CLE_0_CT0CA) !=
-               v3d_hw_read_reg(sim_state.v3d, V3D_CLE_0_CT0EA)) {
-                v3d_hw_tick(sim_state.v3d);
-        }
-
-        v3d_hw_write_reg(sim_state.v3d, V3D_CLE_0_CT1QBA, submit->rcl_start);
-        v3d_hw_write_reg(sim_state.v3d, V3D_CLE_0_CT1QEA, submit->rcl_end);
-
-        while (v3d_hw_read_reg(sim_state.v3d, V3D_CLE_0_CT1CA) !=
-               v3d_hw_read_reg(sim_state.v3d, V3D_CLE_0_CT1EA) ||
-               v3d_hw_read_reg(sim_state.v3d, V3D_CLE_1_CT1CA) !=
-               v3d_hw_read_reg(sim_state.v3d, V3D_CLE_1_CT1EA)) {
-                v3d_hw_tick(sim_state.v3d);
-        }
+        if (sim_state.ver >= 41)
+                v3d41_simulator_flush(sim_state.v3d, submit, file->gmp->ofs);
+        else
+                v3d33_simulator_flush(sim_state.v3d, submit, file->gmp->ofs);
 
         ret = vc5_simulator_unpin_bos(fd, job);
         if (ret)
@@ -607,25 +525,10 @@ vc5_simulator_gem_close_ioctl(int fd, struct drm_gem_close *args)
 static int
 vc5_simulator_get_param_ioctl(int fd, struct drm_vc5_get_param *args)
 {
-        static const uint32_t reg_map[] = {
-                [DRM_VC5_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG,
-                [DRM_VC5_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1,
-                [DRM_VC5_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2,
-                [DRM_VC5_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3,
-                [DRM_VC5_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_0_IDENT0,
-                [DRM_VC5_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_0_IDENT1,
-                [DRM_VC5_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_0_IDENT2,
-        };
-
-        if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) {
-                args->value = v3d_hw_read_reg(sim_state.v3d,
-                                              reg_map[args->param]);
-                return 0;
-        }
-
-        fprintf(stderr, "Unknown DRM_IOCTL_VC5_GET_PARAM(%lld)\n",
-                (long long)args->value);
-        abort();
+        if (sim_state.ver >= 41)
+                return v3d41_simulator_get_param_ioctl(sim_state.v3d, args);
+        else
+                return v3d33_simulator_get_param_ioctl(sim_state.v3d, args);
 }
 
 int
@@ -662,21 +565,7 @@ vc5_simulator_ioctl(int fd, unsigned long request, void *args)
 }
 
 static void
-vc5_simulator_init_regs(void)
-{
-        /* Set OVRTMUOUT to match kernel behavior.
-         *
-         * This means that the texture sampler uniform configuration's tmu
-         * output type field is used, instead of using the hardware default
-         * behavior based on the texture type.  If you want the default
-         * behavior, you can still put "2" in the indirect texture state's
-         * output_type field.
-         */
-        V3D_WRITE(V3D_CTL_0_MISCCFG, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET);
-}
-
-static void
-vc5_simulator_init_global(void)
+vc5_simulator_init_global(const struct v3d_device_info *devinfo)
 {
         mtx_lock(&sim_state.mutex);
         if (sim_state.refcount++) {
@@ -698,6 +587,8 @@ vc5_simulator_init_global(void)
         struct mem_block *b = u_mmAllocMem(sim_state.heap, 4096, GMP_ALIGN2, 0);
         memset(sim_state.mem + b->ofs - sim_state.mem_base, 0xd0, 4096);
 
+        sim_state.ver = v3d_hw_get_version(sim_state.v3d);
+
         mtx_unlock(&sim_state.mutex);
 
         sim_state.fd_map =
@@ -705,13 +596,16 @@ vc5_simulator_init_global(void)
                                         _mesa_hash_pointer,
                                         _mesa_key_pointer_equal);
 
-        vc5_simulator_init_regs();
+        if (sim_state.ver >= 41)
+                v3d41_simulator_init_regs(sim_state.v3d);
+        else
+                v3d33_simulator_init_regs(sim_state.v3d);
 }
 
 void
 vc5_simulator_init(struct vc5_screen *screen)
 {
-        vc5_simulator_init_global();
+        vc5_simulator_init_global(&screen->devinfo);
 
         screen->sim_file = rzalloc(screen, struct vc5_simulator_file);
         struct vc5_simulator_file *sim_file = screen->sim_file;
diff --git a/src/gallium/drivers/vc5/vc5_simulator_wrapper.cpp b/src/gallium/drivers/vc5/vc5_simulator_wrapper.cpp
index 1e3c5c8f8c..5776aea20b 100644
--- a/src/gallium/drivers/vc5/vc5_simulator_wrapper.cpp
+++ b/src/gallium/drivers/vc5/vc5_simulator_wrapper.cpp
@@ -76,6 +76,13 @@ void v3d_hw_tick(struct v3d_hw *hw)
         return hw->tick();
 }
 
+int v3d_hw_get_version(struct v3d_hw *hw)
+{
+        const V3D_HUB_IDENT_T *ident = hw->get_hub_ident();
+
+        return ident->tech_version * 10 + ident->revision;
+}
+
 }
 
 #endif /* USE_VC5_SIMULATOR */
diff --git a/src/gallium/drivers/vc5/vc5_simulator_wrapper.h b/src/gallium/drivers/vc5/vc5_simulator_wrapper.h
index 14009abf6a..8b5dca15ed 100644
--- a/src/gallium/drivers/vc5/vc5_simulator_wrapper.h
+++ b/src/gallium/drivers/vc5/vc5_simulator_wrapper.h
@@ -37,6 +37,7 @@ bool v3d_hw_has_gca(struct v3d_hw *hw);
 uint32_t v3d_hw_read_reg(struct v3d_hw *hw, uint32_t reg);
 void v3d_hw_write_reg(struct v3d_hw *hw, uint32_t reg, uint32_t val);
 void v3d_hw_tick(struct v3d_hw *hw);
+int v3d_hw_get_version(struct v3d_hw *hw);
 
 #ifdef __cplusplus
 }