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authorCraig Topper <craig.topper@gmail.com>2015-01-06 08:59:30 +0000
committerCraig Topper <craig.topper@gmail.com>2015-01-06 08:59:30 +0000
commitf6145affbf810fca24512c1bcb89b9ad8d0aba71 (patch)
tree51a613542153410dbd37f4ccd5f7385e81c85ca6 /utils
parent51e4a66417f7babc25fe6a89dca6c80fc05eae55 (diff)
[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.
Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225256 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r--utils/TableGen/X86RecognizableInstr.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 1ee376e103c..9351fcb0fec 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -956,7 +956,8 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("SSECC", TYPE_IMM3)
TYPE("AVXCC", TYPE_IMM5)
TYPE("AVX512RC", TYPE_IMM32)
- TYPE("brtarget", TYPE_RELv)
+ TYPE("brtarget32", TYPE_RELv)
+ TYPE("brtarget16", TYPE_RELv)
TYPE("brtarget8", TYPE_REL8)
TYPE("f80mem", TYPE_M80FP)
TYPE("lea32mem", TYPE_LEA)
@@ -1212,7 +1213,8 @@ RecognizableInstr::relocationEncodingFromString(const std::string &s,
ENCODING("i64i32imm_pcrel", ENCODING_ID)
ENCODING("i16imm_pcrel", ENCODING_IW)
ENCODING("i32imm_pcrel", ENCODING_ID)
- ENCODING("brtarget", ENCODING_Iv)
+ ENCODING("brtarget32", ENCODING_Iv)
+ ENCODING("brtarget16", ENCODING_Iv)
ENCODING("brtarget8", ENCODING_IB)
ENCODING("i64imm", ENCODING_IO)
ENCODING("offset16_8", ENCODING_Ia)