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authorTim Northover <tnorthover@apple.com>2015-08-03 17:20:10 +0000
committerTim Northover <tnorthover@apple.com>2015-08-03 17:20:10 +0000
commit8927f6cd0f8d7614e8682a2da08f0a9769be9603 (patch)
tree5168233bad37daacbf5e2546bad0e4da60ee12e8 /test/CodeGen
parent268a7555856b12015465c2b5c2e513529f4fb32c (diff)
ARM: prefer allocating VFP regs at stride 4 on Darwin.
This is necessary for WatchOS support, where the compact unwind format assumes this kind of layout. For now we only want this on Swift-like CPUs though, where it's been the Xcode behaviour for ages. Also, since it can expand the prologue we don't want it at -Oz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243884 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r--test/CodeGen/ARM/fold-stack-adjust.ll5
-rw-r--r--test/CodeGen/ARM/vfp-reg-stride.ll33
2 files changed, 34 insertions, 4 deletions
diff --git a/test/CodeGen/ARM/fold-stack-adjust.ll b/test/CodeGen/ARM/fold-stack-adjust.ll
index b62d0dfee07..99174213562 100644
--- a/test/CodeGen/ARM/fold-stack-adjust.ll
+++ b/test/CodeGen/ARM/fold-stack-adjust.ll
@@ -60,8 +60,6 @@ define void @check_vfp_fold() minsize {
; CHECK: vpush {d6, d7, d8, d9}
; CHECK-NOT: sub sp,
; ...
-; CHECK: vldmia r[[GLOBREG]], {d8, d9}
-; ...
; CHECK-NOT: add sp,
; CHECK: vpop {d6, d7, d8, d9}
; CHECKL pop {r[[GLOBREG]], pc}
@@ -82,9 +80,8 @@ define void @check_vfp_fold() minsize {
%var = alloca i8, i32 16
- %tmp = load %bigVec, %bigVec* @var
+ call void asm "", "r,~{d8},~{d9}"(i8* %var)
call void @bar(i8* %var)
- store %bigVec %tmp, %bigVec* @var
ret void
}
diff --git a/test/CodeGen/ARM/vfp-reg-stride.ll b/test/CodeGen/ARM/vfp-reg-stride.ll
new file mode 100644
index 00000000000..5484cc810b0
--- /dev/null
+++ b/test/CodeGen/ARM/vfp-reg-stride.ll
@@ -0,0 +1,33 @@
+; RUN: llc -mcpu=swift -mtriple=thumbv7s-apple-ios -o - %s | FileCheck %s --check-prefix=CHECK-STRIDE4
+; RUN: llc -mcpu=cortex-a57 -mtriple=thumbv7-linux-gnueabihf -o - %s | FileCheck %s --check-prefix=CHECK-GENERIC
+
+define void @test_reg_stride(double %a, double %b) {
+; CHECK-STRIDE4-LABEL: test_reg_stride:
+; CHECK-STRIDE4-DAG: vmov d16, r
+; CHECK-STRIDE4-DAG: vmov d18, r
+
+; CHECK-GENERIC-LABEL: test_reg_stride:
+; CHECK-GENERIC-DAG: vmov.f64 d16, {{d[01]}}
+; CHECK-GENERIC-DAG: vmov.f64 d17, {{d[01]}}
+
+ call void asm "", "~{r0},~{r1},~{d0},~{d1}"()
+ call arm_aapcs_vfpcc void @eat_doubles(double %a, double %b)
+ ret void
+}
+
+define void @test_stride_minsize(float %a, float %b) minsize {
+; CHECK-STRIDE4-LABEL: test_stride_minsize:
+; CHECK-STRIDE4: vmov d2, {{r[01]}}
+; CHECK-STRIDE4: vmov d3, {{r[01]}}
+
+; CHECK-GENERIC-LABEL: test_stride_minsize:
+; CHECK-GENERIC-DAG: vmov.f32 s4, {{s[01]}}
+; CHECK-GENERIC-DAG: vmov.f32 s6, {{s[01]}}
+ call void asm "", "~{r0},~{r1},~{s0},~{s1},~{d0},~{d1}"()
+ call arm_aapcs_vfpcc void @eat_floats(float %a, float %b)
+ ret void
+}
+
+
+declare arm_aapcs_vfpcc void @eat_doubles(double, double)
+declare arm_aapcs_vfpcc void @eat_floats(float, float)