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2018-11-20meson: Add tests to suitesDylan Baker1-1/+2
Meson test has a concepts of suites, which allow tests to be grouped together. This allows for a subtest of tests to be run only (say only the tests for nir). A test can be added to more than one suite, but for the most part I've only added a test to a single suite, though I've added a compiler group that includes nir, glsl, and glcpp tests. To use this you'll need to invoke meson test directly, instead of ninja test (which always runs all targets). it can be invoked as: `meson test -C builddir --suite $suitename` (meson test has addition options that are pretty useful). Tested-By: Gert Wollny <gert.wollny@collabora.com> Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-19i965: Correct L8_UNORM_SRGB table entryGert Wollny1-1/+1
As the name says, the format is an sRGB format. Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-26intel/isl: Add a unit suffixes to some struct fields and variablesJason Ekstrand6-86/+86
I was about to make the claim to someone that every field in isl_surf is either an enum or has explicit units. Then I looked at isl_surf and discovered this claim was wrong. We should fix that. This commit does a few refactors: * Add _B suffixes to some struct fields * Add _B to some variables and parameters * Rename row_pitch_tiles -> row_pitch_tl Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-08-29intel/compiler: Use two components for 1D array image sizesJason Ekstrand1-6/+6
Having the array length component stored in .z was a small convenience for the ISL image param filling code and an annoyance in the NIR lowering code. The only convenience of treating 1D arrays like 2D arrays in the lowering code is in the address calculation code so let's put all the complexity there as well. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29isl: Use the view array length for the image sizeJason Ekstrand1-2/+5
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-22intel/isl: Avoid tiling some 16K-wide render targetsNanley Chery1-0/+23
Fix rendering issues on BDW and SKL. Fixes: 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3 ("i965/miptree: Use the correct BLT pitch") Fixes the following regressions seen exclusively on SKL: * KHR-GL46.texture_barrier_ARB.disjoint-texels * KHR-GL46.texture_barrier_ARB.overlapping-texels * KHR-GL46.texture_barrier.disjoint-texels * KHR-GL46.texture_barrier.overlapping-texels and both on BDW and SKL: * GTF-GL46.gtf21.GL2FixedTests.buffer_corners.buffer_corners * GTF-GL46.gtf21.GL2FixedTests.stencil_plane_corners.stencil_plane_corners v2: Note the fixed tests (Andres). Don't cause failures with multisampled buffers (Andres). Don't hamper SKL GT4 (Ken). v3: Fix the Fixes tag (Dylan). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107359 Cc: <mesa-stable@lists.freedesktop.org> Tested-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-08-16intel: various python cleanupsEric Engestrom1-5/+4
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-10meson: Build with Python 3Mathieu Bridon1-1/+1
Now that all the build scripts are compatible with both Python 2 and 3, we can flip the switch and tell Meson to use the latter. Since Meson already depends on Python 3 anyway, this means we don't need two different Python stacks to build Mesa. Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr> Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-07-19intel/isl/gen4: Make depth/stencil buffers Y-TiledNanley Chery1-1/+8
Rendering to a linear depth buffer on gen4 is causing a GPU hang in the CI system. Until a better explanation is found, assume that errata is applicable to all gen4 platforms. Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e ("i965/miptree: Share tiling_flags in miptree_create"). Reported-by: Mark Janes <mark.a.janes@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248 Tested-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-06-18meson: fix i965/anv/isl genX static lib namesEric Engestrom1-1/+1
Shouldn't make any functional difference, just that `liblibanv_gen90.a` will now be called `libanv_gen90.a`. Fixes: 3218056e0eb375eeda470 "meson: Build i965 and dri stack" Fixes: d1992255bb29054fa5176 "meson: Add build Intel "anv" vulkan driver" Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-06-07intel/isl: Add bounds-checking assertions for the format_info tableJason Ekstrand1-8/+16
We follow the same convention as isl_format_get_layout in having two assertions to ensure that only valid formats are passed in. We also check against the array size of the table because some valid formats such as CCS formats will may be past the end of the table. This fixes some potential out-of-bounds array access even in valid cases. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-06-07intel/isl: Add bounds-checking assertions in isl_format_get_layoutJason Ekstrand2-12/+22
We add two assertions instead of one because the first assertion that format != ISL_FORMAT_UNSUPPORTED is more descriptive and checks for a real but unsupported enumerant while the second ensures that they don't pass in garbage values. We also update some other helpers to use isl_format_get_layout instead of using the table directly so that they get bounds checking too. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-05-18i965: isl: Move the MCS gen7+ assertion into ISLNanley Chery1-0/+2
This is useful for every user of ISL. Drop the comment along the way to match similar functions in ISL. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-10intel/isl/storage: Don't lower most UNORM formats on gen11+Jason Ekstrand1-6/+10
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
2018-05-10intel/isl: Several UNORM formats support typed writes on gen11+Jason Ekstrand1-13/+13
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
2018-05-09intel/isl: Allow CCS_E on 1010102 formatsJason Ekstrand1-11/+0
On CNL and above, CCS_E supports 1010102 formats and R11G11B10F. We had shut them off during early enabling because blorp_copy couldn't handle them. Now it can handle 1010102 formats so we can turn them back on. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09intel/isl: Add format conversion codeJason Ekstrand3-1/+222
This adds helpers to ISL to convert an isl_color_value to and from binary data encoded with a given isl_format. The conversion is done using ISL's built-in format introspection so it's fairly slow as format conversions go but it should be fine for a single pixel value. In particular, we can use this to convert clear colors. As a side-effect, we now rely on the sRGB helpers in libmesautil so we need to tweak the build system a bit. All prior uses of src/util in ISL were header-only. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09intel/isl/format: Get rid of the ALPHA colorspaceJason Ekstrand2-8/+8
Alpha-only formats are just linear. There's no need to specially deliminate them as being in their own colorspace. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09intel/isl/format: Add field locations informations to channel_layoutJason Ekstrand2-2/+13
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09intel/isl/format: Add a column for channel order to the tableJason Ekstrand2-281/+282
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09intel/isl: Add some helpers for working with RGBX formatsJason Ekstrand2-0/+43
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09intel/isl: Add a helper for inverting swizzlesJason Ekstrand2-0/+32
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09intel/isl: Add a helper for composing swizzlesJason Ekstrand2-0/+38
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-05-09intel/isl: Add an isl_swizzle_supports_rendering helperJason Ekstrand3-32/+71
This helper encodes more details, specifically about Haswell, than the previous asserts in isl_surface_state.c. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-05intel/isl: Add support to emit clear value address.Rafael Antognolli2-4/+23
gen10 can emit the clear color by setting it on a buffer somewhere, and then adding only the address to the surface state. This commit add support for that on isl_surf_fill_state, and if that is requested, skip setting the clear value itself. v2: Add assert to make sure we are at least on gen10. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-05intel: Use Clear Color struct size.Rafael Antognolli2-0/+10
The size of the clear color struct (expected by the hardware) is 8 dwords (isl_dev.ss.clear_value_state_size here). But we still need to track the size of the clear color, used when memcopying it to/from the state buffer. For that we keep isl_dev.ss.clear_value_size. v4: - Add struct to gen11 too (Jason, Jordan) - Add field for Converted Clear Color to gen11 (Jason) - Add clear_color_state_offset to differentiate from clear_value_offset. - Fix all the places where clear_value_size was used. v5 (Jason): - Split genxml changes to another commit. - Remove unnecessary gen checks. - Bring back missing offset increment to init_fast_clear_color(). v6 (Jason): - On init_fast_clear_color, change: addr.offset += 4 => sdi.Address.offset += i * 4 - Use GEN_GEN instead of GEN_VERSIONx10. [jordan.l.justen@intel.com: isl_device_init changes] Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-03-05intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke1-3/+3
We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> [jordan.l.justen@intel.com: Minor changes for rebase] Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-03-05intel/isl: Add isl_format_is_validJordan Justen2-0/+10
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-03-05intel: Split gen_device_info out into libintel_devJordan Justen5-5/+5
Split out the device info so isl doesn't depend on intel/common. Now it will depend on the new intel/dev device info lib. This will allow the decoder in intel/common to use isl, allowing us to apply Ken's patch that removes the genxml duplication of surface formats. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-03-02isl: Silence unused parameter warnings in __gen_combine_address implementationsIan Romanick2-2/+6
Reduces my build from 1808 warnings to 1772 warnings by silencing 36 instances of things like ../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c: In function ‘__gen_combine_address’: ../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:30:29: warning: unused parameter ‘data’ [-Wunused-parameter] __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) ^~~~ ../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c:30:41: warning: unused parameter ‘loc’ [-Wunused-parameter] __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) ^~~ Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-02-28isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bitJose Maria Casanova Crespo1-1/+21
The surfaces that backup the GPU buffers have a boundary check that considers that access to partial dwords are considered out-of-bounds. For example, buffers with 1,3 16-bit elements has size 2 or 6 and the last two bytes would always be read as 0 or its writting ignored. The introduction of 16-bit types implies that we need to align the size to 4-bytew multiples so that partial dwords could be read/written. Adding an inconditional +2 size to buffers not being multiple of 2 solves this issue for the general cases of UBO or SSBO. But, when unsized arrays of 16-bit elements are used it is not possible to know if the size was padded or not. To solve this issue the implementation calculates the needed size of the buffer surfaces, as suggested by Jason: surface_size = isl_align(buffer_size, 4) + (isl_align(buffer_size, 4) - buffer_size) So when we calculate backwards the buffer_size in the backend we update the resinfo return value with: buffer_size = (surface_size & ~3) - (surface_size & 3) It is also exposed this buffer requirements when robust buffer access is enabled so these buffer sizes recommend being multiple of 4. v2: (Jason Ekstrand) Move padding logic fron anv to isl_surface_state. Move calculus of original size from spirv to driver backend. v3: (Jason Ekstrand) Rename some variables and use a similar expresion when calculating. padding than when obtaining the original buffer size. Avoid use of unnecesary component call at brw_fs_nir. v4: (Jason Ekstrand) Complete comment with buffer size calculus explanation in brw_fs_nir. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-02-21intel/isl: Improve the documentation on get_default_aux_stateJason Ekstrand1-4/+20
Reviewed-by: Chad Versace <chadversary@chromium.org>
2018-02-20intel/isl: Add an isl_color_value_is_zero helperJason Ekstrand2-0/+23
Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-02-15intel/isl/icl: Build and use gen11 surface state emit functionsAnuj Phogat3-1/+7
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-02-15intel/isl/icl: Add the maximum surface size limitAnuj Phogat1-1/+5
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-02-14isl: Don't use surface format R32_FLOAT for typed atomic integer operationsAnuj Phogat1-1/+8
From Skylake PRM Surface Formats section: "The surface format for the typed atomic integer operations must be R32_UINT or R32_SINT." Fixes an error and a piglit GPU hang in simulation environment. Piglit test: gl45-imageAtomicExchange-float.shader_test Suggested-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.co Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: "18.0 17.3" <mesa-stable@lists.freedesktop.org>
2018-02-08intel/isl: Codify AUX operations in an enumJason Ekstrand1-25/+49
Right now, we have different entrypoints and enums in blorp for these different operations. This provides us a central enum which we can begin to transition to. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-01-11meson: don't use intermediate variables that are immediately discardedDylan Baker1-4/+2
For things like: loop x = func() list += x end just do: loop list += func() end Acked-by: Eric Engestrom <eric.engestrom@imgtec.com> Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
2018-01-11meson: Use consistent style for testsDylan Baker1-8/+9
Don't use intermediate variables, use consistent whitespace. Acked-by: Eric Engestrom <eric.engestrom@imgtec.com> Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
2017-12-15isl: Don't require VALIGN_2 for R32G32B32_FLOAT on Haswell.Kenneth Graunke1-1/+3
According to the RENDER_SURFACE_STATE internal documentation, the R32G32B32_FLOAT restriction is marked "IVB" only. We choose to apply it to Ivybridge and Baytrail, but not Haswell. Apparently fixes KHR-GL46.texture_size_promotion.functional on Haswell. Changes these tests from crashing to skipping on Haswell: - KHR-GL46.direct_state_access.textures_storage_multisample_2d_rgb32f - KHR-GL46.direct_state_access.textures_storage_multisample_3d_rgb32f Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-12-04intel/isl: Declare private array as static constChad Versace1-1/+1
It's array isl_drm.c:modifier_info[] . Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-11-13meson: Don't build intel shared components by defaultDylan Baker1-3/+0
It's a neat idea, and still useful in some cases, but the intel common code is used by i965 and anvil only, this is a little clearer. Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-31intel/isl: Disable some gen10 CCS_E formats for nowNanley Chery1-0/+24
CannonLake additionally supports R11G11B10_FLOAT and four 10-10-10-2 formats with CCS_E. None of these formats fit within the current blorp_copy framework so disable them until support is added. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-19isl: Fix width check in isl_gen7_choose_msaa_layout.Kenneth Graunke1-1/+1
The restriction is supposed to apply if the width *field* is >= 8192, meaning the actual width *value* is >= 8193. The code also incorrectly used == for some reason. Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-12meson: fix typo in isltournier.elie1-1/+1
Signed-off-by: Elie Tournier <elie.tournier@collabora.com> Reviewed-by: Antia Puentes <apuentes@igalia.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-10-06isl: fill out layout descriptions for yuv formatsLionel Landwerlin1-4/+4
Some description was missing. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-06isl: check whether a format is rgb if colorspace is yuvLionel Landwerlin1-0/+2
Suggested by Chad. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-06isl: make format layout channels accessible by indexLionel Landwerlin1-9/+12
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-03intel: Always set Cube Face Enables for all surfaces.Kenneth Graunke1-8/+6
These shouldn't matter for non-cubes, and we always enable them all for cubes, so we may as well set them all the time. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-03intel: Make Cube Face Enable fields consistent across generations.Kenneth Graunke1-4/+0
I decided to use the one-boolean-per-cube-face approach because it's clearer which bits correspond to which cube face. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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