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path: root/src/gallium/drivers
AgeCommit message (Expand)AuthorFilesLines
2018-11-29virgl: fix undefined shift to use unsigned.HEADmasterDave Airlie1-1/+1
2018-11-29r600: make suballocator 256-bytes alignDave Airlie1-1/+1
2018-11-28winsys/amdgpu: explicitly declare whether buffer_map is permanent or notNicolai Hähnle14-28/+67
2018-11-28virgl: Don't try handling server fences when they are not supportedGert Wollny1-2/+4
2018-11-27v3d: Add renderonly support.Eric Anholt4-4/+68
2018-11-27freedreno: implements get_sample_positionHyunjun Ko1-0/+45
2018-11-27freedreno/a3xx: also set FSSUPERTHREADENABLERob Clark1-0/+1
2018-11-27freedreno: use MSM_BO_SCANOUT with scanout buffersJonathan Marek1-1/+3
2018-11-27freedreno: use GENERIC instead of TEXCOORD for blit programJonathan Marek1-1/+1
2018-11-27freedreno: a2xx texture updateJonathan Marek9-20/+212
2018-11-27freedreno/a2xx: Compute depth base in gmem correctlyJonathan Marek1-5/+7
2018-11-27freedreno/a2xx: set VIZ_QUERY_ID on a20xJonathan Marek1-0/+5
2018-11-27freedreno: add missing a20x idsJonathan Marek1-0/+2
2018-11-27freedreno/a2xx: fix POINT_MINMAX_MAX overflowJonathan Marek1-1/+1
2018-11-27freedreno: a2xx: fd2_draw updateJonathan Marek6-20/+114
2018-11-27freedreno: update generated headersRob Clark7-39/+287
2018-11-27freedreno/a6xx: set guardband clipRob Clark4-7/+57
2018-11-27freedreno/a6xx: disable LRZ for z32Rob Clark1-1/+13
2018-11-27freedreno/a6xx: Clear gmem buffers at flush timeKristian H. Kristensen4-178/+180
2018-11-27freedreno/a6xx: Move resolve blits to an IBKristian H. Kristensen3-8/+29
2018-11-27freedreno/a6xx: Move restore blits to IBKristian H. Kristensen3-19/+49
2018-11-27freedreno: move ir3 to common locationRob Clark40-13732/+37
2018-11-27freedreno/ir3: remove u_inlines usageRob Clark1-10/+10
2018-11-27freedreno/ir3: split up ir3_shaderRob Clark14-667/+766
2018-11-27freedreno/ir3: remove pipe_stream_output_info dependencyRob Clark8-17/+68
2018-11-27freedreno/ir3: some header file cleanupRob Clark11-26/+24
2018-11-27freedreno/ir3: use env_var_as_unsigned()Rob Clark2-14/+2
2018-11-27freedreno/ir3: move disasm and optmsgs debug flagsRob Clark9-22/+25
2018-11-27freedreno: FD_SHADER_DEBUG -> IR3_SHADER_DEBUGRob Clark4-33/+34
2018-11-27freedreno: remove shader_stage_name()Rob Clark3-21/+3
2018-11-27freedreno: shader_t -> gl_shader_stageRob Clark22-143/+121
2018-11-27freedreno/ir3: standalone compiler updatesRob Clark1-6/+27
2018-11-27freedreno: move drm to common locationRob Clark20-3717/+12
2018-11-27freedreno/drm: remove dependency on gallium driverRob Clark1-2/+11
2018-11-24nv50/ir: remove dnz flag when converting MAD to ADD due to optimizationsIlia Mirkin1-0/+3
2018-11-21virgl: add assert and missing function parameterRobert Foss1-1/+4
2018-11-21r600: clean up the GS ring buffers when the context is destroyedGert Wollny1-0/+6
2018-11-20radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSEDMarek Olšák1-11/+4
2018-11-20radeonsi: don't send data after write-confirm with BOTTOM_OF_PIPE_TSMarek Olšák3-9/+5
2018-11-20meson: Add tests to suitesDylan Baker2-2/+4
2018-11-19nir: Make nir_lower_clip_vs optionally work with variables.Kenneth Graunke2-2/+3
2018-11-19etnaviv: use dummy RT buffer when rendering without color bufferLucas Stach3-2/+19
2018-11-19radeonsi: fix an out-of-bounds read reported by ASANNicolai Hähnle1-0/+4
2018-11-19r600: Only set context streamout strides info from the shader that has outputsGert Wollny1-3/+9
2018-11-18virgl: Clean up fences commitRobert Foss1-1/+1
2018-11-16nv50/ir/ra: enforce max register requirement, and change spill orderIlia Mirkin4-16/+26
2018-11-16nv50/ir/ra: improve condition for short regs, unify with cond for 16-bitIlia Mirkin1-7/+7
2018-11-16nv50/ir: delete MINMAX instruction that is no longer in the BBIlia Mirkin1-1/+1
2018-11-16virgl: native fence fd supportRobert Foss3-10/+62
2018-11-15vc4: Don't return a vc4 BO handle on a renderonly screen.Eric Anholt1-2/+4
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