freedreno/ir3: move disasm and optmsgs debug flags

Move them to IR3_SHADER_DEBUG so we can remove ir3's dependency on
fd_mesa_debug.

Signed-off-by: Rob Clark <robdclark@gmail.com>

9 files changed, 25 insertions, 22 deletions

diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 2772c109153..79713044b86 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -64,7 +64,7 @@
 
 static const struct debug_named_value debug_options[] = {
 		{"msgs",      FD_DBG_MSGS,   "Print debug messages"},
-		{"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
+		{"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
 		{"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
 		{"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
 		{"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
@@ -72,7 +72,6 @@ static const struct debug_named_value debug_options[] = {
 		{"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
 		{"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
 		{"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
-		{"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
 		{"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
 		{"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
 		{"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
diff --git a/src/gallium/drivers/freedreno/freedreno_util.h b/src/gallium/drivers/freedreno/freedreno_util.h
index 8e063c09966..0017ac5a397 100644
--- a/src/gallium/drivers/freedreno/freedreno_util.h
+++ b/src/gallium/drivers/freedreno/freedreno_util.h
@@ -70,7 +70,7 @@ enum adreno_stencil_op fd_stencil_op(unsigned op);
 #define FD_DBG_NOBYPASS 0x0040
 #define FD_DBG_FRAGHALF 0x0080
 #define FD_DBG_NOBIN    0x0100
-#define FD_DBG_OPTMSGS  0x0200
+/* unused 0x0200 */
 #define FD_DBG_GLSL120  0x0400
 #define FD_DBG_SHADERDB 0x0800
 #define FD_DBG_FLUSH    0x1000
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index bb1133d3c7f..d1e1af0d0b6 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -297,7 +297,7 @@ int main(int argc, char **argv)
 
 	while (n < argc) {
 		if (!strcmp(argv[n], "--verbose")) {
-			fd_mesa_debug |= FD_DBG_MSGS | FD_DBG_OPTMSGS | FD_DBG_DISASM;
+			ir3_shader_debug |= IR3_DBG_OPTMSGS | IR3_DBG_DISASM;
 			n++;
 			continue;
 		}
@@ -452,13 +452,13 @@ int main(int argc, char **argv)
 			return ret;
 		}
 
-		if (fd_mesa_debug & FD_DBG_OPTMSGS)
+		if (ir3_shader_debug & IR3_DBG_OPTMSGS)
 			debug_printf("%s\n", (char *)ptr);
 
 		if (!tgsi_text_translate(ptr, toks, ARRAY_SIZE(toks)))
 			errx(1, "could not parse `%s'", filenames[0]);
 
-		if (fd_mesa_debug & FD_DBG_OPTMSGS)
+		if (ir3_shader_debug & IR3_DBG_OPTMSGS)
 			tgsi_dump(toks, 0);
 
 		nir = ir3_tgsi_to_nir(toks);
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
index c6add971304..f00daebabf5 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
@@ -32,6 +32,8 @@ static const struct debug_named_value shader_debug_options[] = {
 		{"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
 		{"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
 		{"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
+		{"disasm",  IR3_DBG_DISASM, "Dump NIR and adreno shader disassembly"},
+		{"optmsgs", IR3_DBG_OPTMSGS,"Enable optimizer debug messages"},
 		DEBUG_NAMED_VALUE_END
 };
 
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.h b/src/gallium/drivers/freedreno/ir3/ir3_compiler.h
index af663e87bb8..e2336062b29 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.h
@@ -74,6 +74,8 @@ enum ir3_shader_debug {
 	IR3_DBG_SHADER_VS = 0x01,
 	IR3_DBG_SHADER_FS = 0x02,
 	IR3_DBG_SHADER_CS = 0x04,
+	IR3_DBG_DISASM    = 0x08,
+	IR3_DBG_OPTMSGS   = 0x10,
 };
 
 extern enum ir3_shader_debug ir3_shader_debug;
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index a75c6c3a6df..83f9a3605cc 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -181,7 +181,7 @@ compile_init(struct ir3_compiler *compiler,
 	NIR_PASS_V(ctx->s, nir_lower_locals_to_regs);
 	NIR_PASS_V(ctx->s, nir_convert_from_ssa, true);
 
-	if (fd_mesa_debug & FD_DBG_DISASM) {
+	if (ir3_shader_debug & IR3_DBG_DISASM) {
 		DBG("dump nir%dv%d: type=%d, k={cts=%u,hp=%u}",
 			so->shader->id, so->id, so->type,
 			so->key.color_two_side, so->key.half_precision);
@@ -3680,7 +3680,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 		}
 	}
 
-	if (fd_mesa_debug & FD_DBG_OPTMSGS) {
+	if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
 		printf("BEFORE CP:\n");
 		ir3_print(ir);
 	}
@@ -3709,7 +3709,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 		}
 	}
 
-	if (fd_mesa_debug & FD_DBG_OPTMSGS) {
+	if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
 		printf("BEFORE GROUPING:\n");
 		ir3_print(ir);
 	}
@@ -3721,14 +3721,14 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 	 */
 	ir3_group(ir);
 
-	if (fd_mesa_debug & FD_DBG_OPTMSGS) {
+	if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
 		printf("AFTER GROUPING:\n");
 		ir3_print(ir);
 	}
 
 	ir3_depth(ir);
 
-	if (fd_mesa_debug & FD_DBG_OPTMSGS) {
+	if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
 		printf("AFTER DEPTH:\n");
 		ir3_print(ir);
 	}
@@ -3739,7 +3739,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 		goto out;
 	}
 
-	if (fd_mesa_debug & FD_DBG_OPTMSGS) {
+	if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
 		printf("AFTER SCHED:\n");
 		ir3_print(ir);
 	}
@@ -3750,7 +3750,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 		goto out;
 	}
 
-	if (fd_mesa_debug & FD_DBG_OPTMSGS) {
+	if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
 		printf("AFTER RA:\n");
 		ir3_print(ir);
 	}
@@ -3800,7 +3800,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 	 */
 	ir3_legalize(ir, &so->num_samp, &so->has_ssbo, &max_bary);
 
-	if (fd_mesa_debug & FD_DBG_OPTMSGS) {
+	if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
 		printf("AFTER LEGALIZE:\n");
 		ir3_print(ir);
 	}
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
index bb00190ea38..5e79522a82a 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
@@ -161,7 +161,7 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 		tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 	}
 
-	if (fd_mesa_debug & FD_DBG_DISASM) {
+	if (ir3_shader_debug & IR3_DBG_DISASM) {
 		debug_printf("----------------------\n");
 		nir_print_shader(s, stdout);
 		debug_printf("----------------------\n");
@@ -207,7 +207,7 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 
 	OPT_V(s, nir_move_load_const);
 
-	if (fd_mesa_debug & FD_DBG_DISASM) {
+	if (ir3_shader_debug & IR3_DBG_DISASM) {
 		debug_printf("----------------------\n");
 		nir_print_shader(s, stdout);
 		debug_printf("----------------------\n");
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_ra.c b/src/gallium/drivers/freedreno/ir3/ir3_ra.c
index 3218d92815d..8dfa8195606 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_ra.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_ra.c
@@ -867,7 +867,7 @@ ra_add_interference(struct ir3_ra_ctx *ctx)
 	/* update per-block livein/liveout: */
 	while (ra_compute_livein_liveout(ctx)) {}
 
-	if (fd_mesa_debug & FD_DBG_OPTMSGS) {
+	if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
 		debug_printf("AFTER LIVEIN/OUT:\n");
 		ir3_print(ir);
 		list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
index c13c47ce499..14605902458 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
@@ -143,7 +143,7 @@ assemble_variant(struct ir3_shader_variant *v)
 
 	memcpy(fd_bo_map(v->bo), bin, sz);
 
-	if (fd_mesa_debug & FD_DBG_DISASM) {
+	if (ir3_shader_debug & IR3_DBG_DISASM) {
 		struct ir3_shader_key key = v->key;
 		printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
 			v->binning_pass, key.color_two_side, key.half_precision);
@@ -327,7 +327,7 @@ ir3_shader_create(struct ir3_compiler *compiler,
 		nir = cso->ir.nir;
 	} else {
 		debug_assert(cso->type == PIPE_SHADER_IR_TGSI);
-		if (fd_mesa_debug & FD_DBG_DISASM) {
+		if (ir3_shader_debug & IR3_DBG_DISASM) {
 			DBG("dump tgsi: type=%d", shader->type);
 			tgsi_dump(cso->tokens, 0);
 		}
@@ -337,7 +337,7 @@ ir3_shader_create(struct ir3_compiler *compiler,
 			   (nir_lower_io_options)0);
 	/* do first pass optimization, ignoring the key: */
 	shader->nir = ir3_optimize_nir(shader, nir, NULL);
-	if (fd_mesa_debug & FD_DBG_DISASM) {
+	if (ir3_shader_debug & IR3_DBG_DISASM) {
 		DBG("dump nir%d: type=%d", shader->id, shader->type);
 		nir_print_shader(shader->nir, stdout);
 	}
@@ -378,7 +378,7 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
 			   (nir_lower_io_options)0);
 	} else {
 		debug_assert(cso->ir_type == PIPE_SHADER_IR_TGSI);
-		if (fd_mesa_debug & FD_DBG_DISASM) {
+		if (ir3_shader_debug & IR3_DBG_DISASM) {
 			DBG("dump tgsi: type=%d", shader->type);
 			tgsi_dump(cso->prog, 0);
 		}
@@ -387,7 +387,7 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
 
 	/* do first pass optimization, ignoring the key: */
 	shader->nir = ir3_optimize_nir(shader, nir, NULL);
-	if (fd_mesa_debug & FD_DBG_DISASM) {
+	if (ir3_shader_debug & IR3_DBG_DISASM) {
 		printf("dump nir%d: type=%d\n", shader->id, shader->type);
 		nir_print_shader(shader->nir, stdout);
 	}