summaryrefslogtreecommitdiff
path: root/src/freedreno/ir3/ir3.c
AgeCommit message (Expand)AuthorFilesLines
2020-04-18ir3/ra: Fix off-by-one issues with live-range extensionConnor Abbott1-1/+23
2020-04-15ir3: Fix LDC offset unitsConnor Abbott1-1/+1
2020-04-13freedreno/ir3: rename depth->dceRob Clark1-1/+0
2020-04-13freedreno/ir3: add mov/cov statsRob Clark1-3/+8
2020-04-13freedreno/ir3: make falsedep use's optionalRob Clark1-2/+4
2020-04-09ir3: Plumb through bindless supportConnor Abbott1-13/+45
2020-04-09ir3: LDC also has a destinationConnor Abbott1-1/+1
2020-04-09ir3: Plumb through support for a1.xConnor Abbott1-1/+8
2020-04-09ir3: Add bindless instruction encodingConnor Abbott1-22/+23
2020-04-04freedreno/ir3: add a pass to collect SSA usesRob Clark1-0/+24
2020-03-10freedreno/ir3: add simplified stall estimationRob Clark1-1/+11
2020-02-28freedreno/ir3: fix assert with getinfoRob Clark1-2/+3
2020-02-01freedreno/ir3: remove unused tex arg harderRob Clark1-14/+6
2020-02-01freedreno/ir3: number instructions from oneRob Clark1-1/+1
2020-01-15freedreno/ir3: rename instructionsRob Clark1-1/+8
2019-12-13freedreno/ir3: add iterator macrosRob Clark1-9/+9
2019-12-13freedreno/ir3: add last-baryf shaderdb statRob Clark1-0/+4
2019-11-12freedreno/ir3: re-work shader inputs/outputsRob Clark1-7/+1
2019-11-12freedreno/ir3: fix valgrind complaint with STLWRob Clark1-1/+1
2019-11-09freedreno/ir3: also track # of nops for shader-dbRob Clark1-0/+3
2019-11-07freedreno/ir3: Add new synchronization opcodesKristian H. Kristensen1-0/+3
2019-11-07freedreno/a6xx: Add register offset for STG/LDGKristian H. Kristensen1-7/+26
2019-10-24freedreno/ir3: remove restrictions on const + (abs)/(neg)Rob Clark1-4/+6
2019-10-17freedreno/ir3: Add new LDLW/STLW instructionsKristian H. Kristensen1-2/+2
2019-10-17freedreno/ir3: Use third register for offset for LDL and LDLVKristian H. Kristensen1-5/+9
2019-09-16freedreno: Fix invalid read when a block has no instructions.Eric Anholt1-2/+3
2019-09-06freedreno/ir3: assert that only single addressRob Clark1-0/+4
2019-07-29freedreno: Fix data races with allocating/freeing struct ir3.Eric Anholt1-1/+1
2019-04-30freedreno/ir3: fixes for half reg in/outRob Clark1-7/+7
2019-04-25freedreno/ir3: remove bogus assertRob Clark1-2/+0
2019-04-25freedreno/ir3: more emit-cat5 fixesRob Clark1-0/+2
2019-03-28freedreno/ir3: Add workaround for VS samgqKristian H. Kristensen1-1/+2
2019-03-28freedreno/ir3: Don't access beyond available regsKristian H. Kristensen1-4/+7
2019-03-25freedreno/ir3: Fix operand order for DSX/DSYKristian H. Kristensen1-0/+15
2019-03-21freedreno/ir3: fix regmask for merged regsRob Clark1-0/+3
2019-03-21freedreno/ir3: fix sam.s2en encodingRob Clark1-9/+9
2019-03-03freedreno/ir3: include nopN in expanded instruction countRob Clark1-1/+1
2019-02-26freedreno/ir3: use nopN encoding when possibleRob Clark1-5/+23
2019-02-20freedreno/ir3: sync instr/disasm and add ldib encodingRob Clark1-2/+17
2019-02-16freedreno/ir3: add a6xx instruction encodingRob Clark1-0/+90
2018-11-27freedreno: move ir3 to common locationRob Clark1-0/+941
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 21:30:55 +0000