diff options
| author | Ilia Mirkin <imirkin@alum.mit.edu> | 2017-04-08 14:56:16 -0400 |
|---|---|---|
| committer | Ilia Mirkin <imirkin@alum.mit.edu> | 2017-04-11 00:13:55 -0400 |
| commit | 8036809799c453b02f4c8fedbb5faaeb19af90c2 (patch) | |
| tree | c5933443c180afe45f260305e94737ec7e870e6f /src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | |
| parent | 8ffd54fef838784ef4388d48843cddf55246e529 (diff) | |
nvc0: increase texture buffer object alignment to 256 for pre-GM107
We currently don't pass the low byte of the address via the surface
info, so in order to work with images, these have to implicitly be
aligned to 256. The proprietary driver also doesn't go out of its way to
provide lower alignment.
Fixes GL45-CTS.texture_buffer.texture_buffer_texture_buffer_range
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Diffstat (limited to 'src/gallium/drivers/nouveau/nvc0/nvc0_screen.c')
| -rw-r--r-- | src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 7ef9bf9c9cf3..da5561f53a56 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -147,7 +147,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: return 256; case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: - if (class_3d < NVE4_3D_CLASS) + if (class_3d < GM107_3D_CLASS) return 256; /* IMAGE bindings require alignment to 256 */ return 16; case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: |