diff options
| author | Ian Romanick <ian.d.romanick@intel.com> | 2019-02-26 15:52:57 -0800 |
|---|---|---|
| committer | Ian Romanick <ian.d.romanick@intel.com> | 2019-03-26 10:29:22 -0700 |
| commit | bf8b7fef31a3eaea6a6f152ec0c8a5b3d8727589 (patch) | |
| tree | 85bc063cc35ab67da0d2b261218dec14f82c4557 | |
| parent | e74b9e0776ac1fee72cc96d52ed4e5949227b343 (diff) | |
logic ops
squash! WIP: intel/compiler: Import Gen8 / Gen9 ALU machine description
| -rw-r--r-- | src/intel/compiler/gen8_md.py | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/intel/compiler/gen8_md.py b/src/intel/compiler/gen8_md.py index 0fbe2160bce..32063644355 100644 --- a/src/intel/compiler/gen8_md.py +++ b/src/intel/compiler/gen8_md.py @@ -167,6 +167,62 @@ gen8_md = [ Instruction('ADD', r, r, b).predicate())) ), + # Logic operations + (('inot', 'a(neg_or_abs_src_mod)'), InstructionList([(t0, result_type), ], + (Instruction('MOV', t0, a), + Instruction('NOT', r, t0))) + ), + (('inot', 'a(no_src_mod)'), Instruction('NOT', r, a)), + + # Smash all of the sources and destination to be signed. This doesn't + # matter for the operation of the instruction, but cmod propagation fails + # on unsigned sources with negation (due to fs_inst::can_do_cmod returning + # false). + # + # FINISHME: Add the missing src_mod cases + (('inot@8', ('ixor', 'a(no_src_mod)', 'b(no_src_mod)')), Instruction('XOR', retype(r, B), retype(neg(a), B), retype(b, B))), + (('inot@16', ('ixor', 'a(no_src_mod)', 'b(no_src_mod)')), Instruction('XOR', retype(r, W), retype(neg(a), W), retype(b, W))), + (('inot@32', ('ixor', 'a(no_src_mod)', 'b(no_src_mod)')), Instruction('XOR', retype(r, D), retype(neg(a), D), retype(b, D))), + (('inot@8', ('iand', 'a(no_src_mod)', 'b(no_src_mod)')), Instruction('OR', retype(r, B), retype(neg(a), B), retype(neg(b), B))), + (('inot@16', ('iand', 'a(no_src_mod)', 'b(no_src_mod)')), Instruction('OR', retype(r, W), retype(neg(a), W), retype(neg(b), W))), + (('inot@32', ('iand', 'a(no_src_mod)', 'b(no_src_mod)')), Instruction('OR', retype(r, D), retype(neg(a), D), retype(neg(b), D))), + (('inot@8', ('ior', 'a(no_src_mod)', 'b(no_src_mod)')), Instruction('AND', retype(r, B), retype(neg(a), B), retype(neg(b), B))), + (('inot@16', ('ior', 'a(no_src_mod)', 'b(no_src_mod)')), Instruction('AND', retype(r, W), retype(neg(a), W), retype(neg(b), W))), + (('inot@32', ('ior', 'a(no_src_mod)', 'b(no_src_mod)')), Instruction('AND', retype(r, D), retype(neg(a), D), retype(neg(b), D))), + + (('ixor', 'a(neg_or_abs_src_mod)', 'b(neg_or_abs_src_mod)'), InstructionList([(t0, result_type), (t1, result_type)], + (Instruction('MOV', t0, a), + Instruction('MOV', t1, b), + Instruction('XOR', r, t0, t1))) + ), + (('ixor', 'a(neg_or_abs_src_mod)', 'b(no_src_mod)'), InstructionList([(t0, result_type), ], + (Instruction('MOV', t0, a), + Instruction('XOR', r, t0, b))) + ), + (('ixor', 'a(no_src_mod)', 'b(no_src_mod)'), Instruction('XOR', r, a, b)), + + (('ior', 'a(neg_or_abs_src_mod)', 'b(neg_or_abs_src_mod)'), InstructionList([(t0, result_type), (t1, result_type)], + (Instruction('MOV', t0, a), + Instruction('MOV', t1, b), + Instruction('OR', r, t0, t1))) + ), + (('ior', 'a(neg_or_abs_src_mod)', 'b(no_src_mod)'), InstructionList([(t0, result_type), ], + (Instruction('MOV', t0, a), + Instruction('OR', r, t0, b))) + ), + (('ior', 'a(no_src_mod)', 'b(no_src_mod)'), Instruction('OR', r, a, b)), + + (('iand', 'a(neg_or_abs_src_mod)', 'b(neg_or_abs_src_mod)'), InstructionList([(t0, result_type), (t1, result_type)], + (Instruction('MOV', t0, a), + Instruction('MOV', t1, b), + Instruction('AND', r, t0, t1))) + ), + (('iand', 'a(neg_or_abs_src_mod)', 'b(no_src_mod)'), InstructionList([(t0, result_type), ], + (Instruction('MOV', t0, a), + Instruction('AND', r, t0, b))) + ), + (('iand', 'a(no_src_mod)', 'b(no_src_mod)'), Instruction('AND', r, a, b)), + # Comparisons (('feq32', 'a@64', 'b@64'), InstructionList([(t0, DF),], (Instruction('CMP', t0, a, b).cmod('Z'), |