Import i915 and i965 dri drivers from mesa 7.2.0.7.2.0

3 files changed, 12 insertions, 7 deletions

diff --git a/i965/brw_eu_emit.c b/i965/brw_eu_emit.c
index 6b97f8b..0bfbec9 100644
--- a/i965/brw_eu_emit.c
+++ b/i965/brw_eu_emit.c
@@ -513,6 +513,8 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
    insn->header.compression_control = BRW_COMPRESSION_NONE;
    insn->header.predicate_control = BRW_PREDICATE_NORMAL;
    insn->header.mask_control = BRW_MASK_ENABLE;
+   if (!p->single_program_flow)
+       insn->header.thread_control = BRW_THREAD_SWITCH;
 
    p->current->header.predicate_control = BRW_PREDICATE_NONE;
 
@@ -538,6 +540,8 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
    insn->header.compression_control = BRW_COMPRESSION_NONE;
    insn->header.execution_size = if_insn->header.execution_size;
    insn->header.mask_control = BRW_MASK_ENABLE;
+   if (!p->single_program_flow)
+       insn->header.thread_control = BRW_THREAD_SWITCH;
 
    /* Patch the if instruction to point at this instruction.
     */
@@ -579,6 +583,7 @@ void brw_ENDIF(struct brw_compile *p,
       insn->header.compression_control = BRW_COMPRESSION_NONE;
       insn->header.execution_size = patch_insn->header.execution_size;
       insn->header.mask_control = BRW_MASK_ENABLE;
+      insn->header.thread_control = BRW_THREAD_SWITCH;
 
       assert(patch_insn->bits3.if_else.jump_count == 0);
 
@@ -617,7 +622,7 @@ struct brw_instruction *brw_BREAK(struct brw_compile *p)
    brw_set_src1(insn, brw_imm_d(0x0));
    insn->header.compression_control = BRW_COMPRESSION_NONE;
    insn->header.execution_size = BRW_EXECUTE_8;
-   insn->header.mask_control = BRW_MASK_DISABLE;
+   /* insn->header.mask_control = BRW_MASK_DISABLE; */
    insn->bits3.if_else.pad0 = 0;
    return insn;
 }
@@ -631,7 +636,7 @@ struct brw_instruction *brw_CONT(struct brw_compile *p)
    brw_set_src1(insn, brw_imm_d(0x0));
    insn->header.compression_control = BRW_COMPRESSION_NONE;
    insn->header.execution_size = BRW_EXECUTE_8;
-   insn->header.mask_control = BRW_MASK_DISABLE;
+   /* insn->header.mask_control = BRW_MASK_DISABLE; */
    insn->bits3.if_else.pad0 = 0;
    return insn;
 }
@@ -655,7 +660,7 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
       insn->header.execution_size = execute_size;
       insn->header.predicate_control = BRW_PREDICATE_NONE;
       /* insn->header.mask_control = BRW_MASK_ENABLE; */
-      insn->header.mask_control = BRW_MASK_DISABLE;
+      /* insn->header.mask_control = BRW_MASK_DISABLE; */
 
       return insn;
    }
@@ -694,7 +699,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
 
 /*    insn->header.mask_control = BRW_MASK_ENABLE; */
 
-   insn->header.mask_control = BRW_MASK_DISABLE;
+   /* insn->header.mask_control = BRW_MASK_DISABLE; */
    p->current->header.predicate_control = BRW_PREDICATE_NONE;   
    return insn;
 }
diff --git a/i965/brw_wm_glsl.c b/i965/brw_wm_glsl.c
index 305100f..8dce40f 100644
--- a/i965/brw_wm_glsl.c
+++ b/i965/brw_wm_glsl.c
@@ -850,20 +850,20 @@ static void emit_sop(struct brw_wm_compile *c,
     struct brw_reg dst, src0, src1;
     int i;
 
-    brw_push_insn_state(p);
     for (i = 0; i < 4; i++) {
 	if (mask & (1<<i)) {
 	    dst = get_dst_reg(c, inst, i, 1);
 	    src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 	    src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
+	    brw_push_insn_state(p);
 	    brw_CMP(p, brw_null_reg(), cond, src0, src1);
 	    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 	    brw_MOV(p, dst, brw_imm_f(0.0));
 	    brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 	    brw_MOV(p, dst, brw_imm_f(1.0));
+	    brw_pop_insn_state(p);
 	}
     }
-    brw_pop_insn_state(p);
 }
 
 static void emit_slt(struct brw_wm_compile *c,
diff --git a/i965/brw_wm_surface_state.c b/i965/brw_wm_surface_state.c
index 2ba3eb4..37c6b52 100644
--- a/i965/brw_wm_surface_state.c
+++ b/i965/brw_wm_surface_state.c
@@ -138,7 +138,7 @@ static GLuint translate_tex_format( GLuint mesa_format, GLenum depth_mode )
    case MESA_FORMAT_SRGB_DXT1:
       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 
-   case MESA_FORMAT_Z24_S8:
+   case MESA_FORMAT_S8_Z24:
       return BRW_SURFACEFORMAT_I24X8_UNORM;
 
    default: