diff options
| author | Luc Verhaegen <libv@skynet.be> | 2010-04-02 15:26:00 +0200 |
|---|---|---|
| committer | Luc Verhaegen <libv@skynet.be> | 2010-04-02 15:26:00 +0200 |
| commit | fbde7e04fb8b4b7f1161c2f360c4a30f96e8df51 (patch) | |
| tree | b99fdd6cf7fbafb876ac87482215a84343b3b7e5 | |
| parent | 13aef816195566da5a0337cef972ef6a35fd7336 (diff) | |
Import i915 and i965 dri drivers from mesa 7.7.1.7.7.1
| -rw-r--r-- | i915/intel_tris.c | 4 | ||||
| -rw-r--r-- | shared/intel_reg.h | 4 |
2 files changed, 5 insertions, 3 deletions
diff --git a/i915/intel_tris.c b/i915/intel_tris.c index 65db947..5aefe45 100644 --- a/i915/intel_tris.c +++ b/i915/intel_tris.c @@ -254,7 +254,7 @@ void intel_flush_prim(struct intel_context *intel) BEGIN_BATCH(5, LOOP_CLIPRECTS); OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(0) | I1_LOAD_S(1) | 1); - assert((offset & !S0_VB_OFFSET_MASK) == 0); + assert((offset & ~S0_VB_OFFSET_MASK) == 0); OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, offset); OUT_BATCH((intel->vertex_size << S1_VERTEX_WIDTH_SHIFT) | (intel->vertex_size << S1_VERTEX_PITCH_SHIFT)); @@ -273,7 +273,7 @@ void intel_flush_prim(struct intel_context *intel) OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(0) | I1_LOAD_S(2) | 1); /* S0 */ - assert((offset & !S0_VB_OFFSET_MASK_830) == 0); + assert((offset & ~S0_VB_OFFSET_MASK_830) == 0); OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, offset | (intel->vertex_size << S0_VB_PITCH_SHIFT_830) | S0_VB_ENABLE_830); diff --git a/shared/intel_reg.h b/shared/intel_reg.h index d19f1ba..36d8180 100644 --- a/shared/intel_reg.h +++ b/shared/intel_reg.h @@ -70,8 +70,10 @@ /** @{ * 915 definitions + * + * 915 documents say that bits 31:28 and 1 are "undefined, must be zero." */ -#define S0_VB_OFFSET_MASK 0xffffffc0 +#define S0_VB_OFFSET_MASK 0x0ffffffc #define S0_AUTO_CACHE_INV_DISABLE (1<<0) /** @} */ |