summaryrefslogtreecommitdiff
path: root/src/intel/intel_gpgpu.c
AgeCommit message (Expand)AuthorFilesLines
2015-05-04Revert "CL/Driver: enable atomics in L3 for HSW."Zhigang Gong1-10/+1
2015-05-04CHV: Add cherryview support in the runtime.Meng Mengmeng1-1/+4
2015-04-10runtime: Enhance the error handling when flush gpgpu command queue.Zhigang Gong1-10/+3
2015-02-09SKL: fix some 3D and 2D array image fail.Yang Rong1-2/+2
2015-01-30SKL: Add function intel_gpgpu_bind_image_gen9.Yang Rong1-1/+83
2015-01-30SKL: add skl select_pipeline and cache_control functions.Yang Rong1-2/+24
2015-01-30SKL: Add the function gen9' intel_build_idrt.Yang Rong1-1/+45
2015-01-30SKL: correct the pipe control struct.Yang Rong1-2/+21
2015-01-30SKL: enable skl device.Yang Rong1-1/+69
2015-01-13Fix the printf buffer size bug.Junyan He1-1/+4
2015-01-09CL/Driver/HSW: Convert L3 cycle for texture to uncachable.Zhigang Gong1-1/+1
2015-01-07CL/Driver: quick fix regression caused by remove MI_FLUSH.Zhigang Gong1-0/+2
2015-01-07CL/Driver: enable atomics in L3 for HSW.Zhigang Gong1-1/+10
2015-01-06Remove obsolete MI_FLUSHZhenyu Wang1-1/+3
2014-12-29Separate flush and invalidate in function intel_gpgpu_pipe_control.Yang, Rong1-1/+35
2014-12-25Remove deprecated fulsim codeZhenyu Wang1-16/+1
2014-12-25fix min_max_read_image_args and min_max_parameter_size issue.Luo Xionghu1-1/+1
2014-12-18GBE/CL: use 2D image to implement large image1D_buffer.Zhigang Gong1-1/+1
2014-11-28fix issue to pass utest of runtime_climage_from_boname for BDWGuo Yejun1-2/+2
2014-11-27fix issue to create cl image from libva with non-zero offsetGuo Yejun1-2/+2
2014-11-18Change the IVB/HSW L3 SQC credit setting.Yang Rong1-2/+2
2014-11-12runtime: fix one bug in BDW image.Zhigang Gong1-2/+4
2014-11-11License: adjust all license version to LGPL v2.1+.Zhigang Gong1-1/+1
2014-11-11Revert "fix issue to create cl image from libva with non-zero offset"Zhigang Gong1-4/+4
2014-11-10fix issue to create cl image from libva with non-zero offsetGuo Yejun1-4/+4
2014-11-07BDW: Set the URB/REST size to 384K/384K when SLM disable.Yang Rong1-1/+2
2014-10-31Remove intel_gpgpu_check_binded_buf_address()Zhenyu Wang1-9/+10
2014-10-29IVB/HSW/BYT: Revert the Dynamic state Base Addr and relative buffers address ...Yang Rong1-7/+45
2014-10-28Fix a size assert when setup bti.Yang Rong1-1/+9
2014-10-28Refine the intel gpgpu delete.Yang Rong1-55/+72
2014-10-24Fix AUX buffer for page alignmentZhenyu Wang1-3/+6
2014-10-23Fix the bug of 1D array slice pitchJunyan He1-1/+1
2014-10-16BDW: Also need set Shader Channel Select for constant buffer in BDW.Yang Rong1-0/+6
2014-10-15Fix a HSW constant buffer regression.Yang Rong1-1/+35
2014-10-10Modify the bind sampler logic for gen8Junyan He1-5/+135
2014-10-10BDW: Need not restore SLM setting in BDW.Yang Rong1-3/+3
2014-10-10BDW: Correct scratch buffer of BDW.Yang Rong1-4/+18
2014-10-10BDW: enable SLM in BDW.Yang Rong1-19/+32
2014-10-10BDW: add some BDW function.Yang Rong1-22/+154
2014-10-10BDW: Refine intel_gpgpu_setup_bti and add intel_gpgpu_set_base_address for BDW.Yang Rong1-97/+89
2014-10-10BDW: Add function intel_gpgpu_bind_buf for gen8.Junyan He1-9/+27
2014-10-10BDW: Correct surface base address set in setup bti.Junyan He1-3/+3
2014-10-10BDW: Add function intel_gpgpu_setup_bti for gen8.Junyan He1-0/+39
2014-09-04GBE: fixup/refine a bug for image1D array's extra binding index handling.Zhigang Gong1-9/+19
2014-08-12Fail gracefully on unsupported hardwareRebecca Palmer1-2/+0
2014-07-30GBE: Handle bti allocation for internal buffer used by printf.Ruiling Song1-2/+2
2014-07-30GBE: Refine bti usage in backend & runtime.Ruiling Song1-36/+35
2014-07-30runtime: set correct state for constant buffer on hsw.Ruiling Song1-2/+41
2014-07-15GBE: Optimize constant load with sampler.Ruiling Song1-1/+1
2014-07-11runtime/driver: refine error handlings.Zhigang Gong1-13/+40
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-03 23:57:42 +0000