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2015-05-19Remove some LGPL incompatible code.Zhigang Gong4-1449/+0
2015-05-18Fix a indirect register bug.Yang Rong1-1/+2
2015-05-15CHV: Fix a chv long convert bug.Yang Rong1-4/+4
2015-05-15GBE: remove unnecessary assertRuiling Song2-2/+0
2015-05-15GBE: Fix the immediate data typeRuiling Song2-7/+7
2015-05-15GBE: make all memory operation share same bti dependency.Ruiling Song1-22/+17
2015-05-15correct the src output of alu3 when OCL_OUTPUT_ASM=1Guo Yejun1-3/+12
2015-05-15add environment variable OCL_OUTPUT_KERNEL_SOURCE.Luo Xionghu1-0/+9
2015-05-15Add Indirect struct argument read support.Yang Rong8-36/+257
2015-05-12rename __gen_ocl_simd_any/all to sub_group_any/allGuo Yejun5-12/+8
2015-05-12add sub group functions intel_sub_group_shuffleGuo Yejun9-3/+81
2015-05-12rename __gen_ocl_get_simd_id/size to get_sub_group_id/sizeGuo Yejun2-4/+9
2015-05-12GBE: fix LOD initialization for typed write instruction.Zhigang Gong1-1/+1
2015-05-12Fix two argument lowering bug.Yang Rong1-4/+7
2015-05-04Chv: Add chv backend support.Yang Rong5-10/+193
2015-05-04CHV: Add cherryview support in the runtime.Meng Mengmeng3-4/+15
2015-04-30Allow building with Python 3Rebecca N. Palmer1-11/+12
2015-04-29Make tgamma meet the accuracy standard.Rebecca N. Palmer1-7/+89
2015-04-24add simd level function __gen_ocl_get_simd_idGuo Yejun12-3/+38
2015-04-24add simd level function __gen_ocl_get_simd_sizeGuo Yejun12-1/+140
2015-04-14Kill the A0 cache in GenContext.Junyan He3-82/+24
2015-04-14GBE: should initialize useDWLabel to false by default.Zhigang Gong1-1/+1
2015-04-13BDW: Refine unpacked_ud in the gen8_context.cpp.Yang Rong1-16/+19
2015-04-13GBE: fix a bug in byte scatter write.Zhigang Gong1-5/+11
2015-04-13GBE: fix an potential assertion in constant expanding pass.Zhigang Gong1-1/+1
2015-04-13GBE: correct the instruction replacement logic in scalarize pass.Zhigang Gong1-9/+34
2015-04-13GBE: Use actual bti information to determine a pointer's addressspace.Zhigang Gong5-8/+23
2015-04-13GBE: Extend front label ip to 32 bit on demand.Zhigang Gong9-25/+116
2015-04-13GBE: don't type cast register/labelindex to integer.Zhigang Gong3-33/+32
2015-04-13GBE: extend backend label to 32 bit.Zhigang Gong3-15/+15
2015-04-13GBE: extend registers/tuples/immediates to 32bit wide.Zhigang Gong7-29/+30
2015-04-13GBE: fix safe type definition.Zhigang Gong1-1/+1
2015-04-13strip unsupported attributes and calling conventions.Zhigang Gong6-4/+134
2015-04-10GBE: avoid to use the GenRegister::xxxgrf(simdWidth,xxx).Zhigang Gong1-47/+46
2015-04-10GBE: correct some temporary virtual register's simdWidth.Zhigang Gong2-12/+19
2015-03-24Use matching versions of clang/llvm and libclang/libllvmRebecca Palmer1-5/+5
2015-03-24BDW: Refine I64HADD and I64RHADD.Yang Rong2-114/+23
2015-03-18Generate NAN for UNDEF value in printf parser.Junyan He1-0/+6
2015-03-17strip PointerCast for call instructions before use.Luo Xionghu2-4/+3
2015-03-16GBE: fix an image related bugs.Zhigang Gong2-17/+24
2015-03-13reset the SPIR target datalayout.Luo Xionghu1-0/+4
2015-03-13Revert "libocl: using mad() to implement dot()"Zhigang Gong1-3/+3
2015-03-12replace pow with llvm intrinsic.Luo Xionghu3-11/+10
2015-03-12replace mad with llvm intrinsic.Luo Xionghu3-11/+1
2015-03-12replace rndd with llvm intrinsic.Luo Xionghu4-5/+4
2015-03-12replace rndu with llvm intrinsic.Luo Xionghu4-5/+2
2015-03-12replace rnde with llvm intrinsic.Luo Xionghu4-5/+4
2015-03-12replace rndz with llvm intrinsic.Luo Xionghu4-5/+2
2015-03-12replace fabs with llvm intrinsic.Luo Xionghu4-5/+2
2015-03-12Backend: Fix errors in disasm for indirect instruction Gen8.Junyan He1-21/+9
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