diff options
| author | Zhigang Gong <zhigang.gong@intel.com> | 2014-06-26 12:38:09 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-06-26 13:09:42 +0800 |
| commit | 68fc4e227a40c7e8dbe4138ff7a859042e2c5027 (patch) | |
| tree | eea6fed3dc7f42b7d95232c7c7861c34fc905b6a /docs/Beignet | |
| parent | a71be6ab76a1ecdc1c8e262f6b775effa49261cc (diff) | |
docs: fix some markdown links and correct some information.
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Diffstat (limited to 'docs/Beignet')
| -rw-r--r-- | docs/Beignet/Backend/TODO.mdwn | 4 | ||||
| -rw-r--r-- | docs/Beignet/Backend/compiler_backend.mdwn | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/docs/Beignet/Backend/TODO.mdwn b/docs/Beignet/Backend/TODO.mdwn index 7651c852..501c5082 100644 --- a/docs/Beignet/Backend/TODO.mdwn +++ b/docs/Beignet/Backend/TODO.mdwn @@ -55,7 +55,7 @@ The code is defined in `src/ir`. Main things to do are: all have a constant data length. - Finishing the handling of function arguments (see the [[IR - description|gen\_ir]] for more details) + description|gen_ir]] for more details) - Merging of independent uniform loads (and samples). This is a major performance improvement once the uniform analysis is done. Basically, several @@ -73,7 +73,7 @@ Backend The code is defined in `src/backend`. Main things to do are: -- Optimize register spilling (see the [[compiler backend description|compiler\_backend]] for more details) +- Optimize register spilling (see the [[compiler backend description|compiler_backend]] for more details) - Implementing proper instruction selection. A "simple" tree matching algorithm should provide good results for Gen diff --git a/docs/Beignet/Backend/compiler_backend.mdwn b/docs/Beignet/Backend/compiler_backend.mdwn index c291fe48..3c489b2f 100644 --- a/docs/Beignet/Backend/compiler_backend.mdwn +++ b/docs/Beignet/Backend/compiler_backend.mdwn @@ -5,7 +5,7 @@ Well, the complete code base is somehow a compiler backend for LLVM. Here, we really speak about the final code generation passes that you may find in `src/backend`. -As explained in [[the scalar IR presentation|gen\_ir]], we bet on a very +As explained in [[the scalar IR presentation|gen_ir]], we bet on a very simple scalar IR to make it easy to parse and modify. The idea is to fix the unrelated problem (very Gen specific) where we can i.e. when the code is generated. |