BDW: Add BDW pci ids and BDW device struct.

Signed-off-by: Yang Rong <rong.r.yang@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Reviewed-by: Junyan He <junyan.he@linux.intel.com>

2 files changed, 136 insertions, 4 deletions

diff --git a/src/cl_device_data.h b/src/cl_device_data.h
index 28bd5f00..29827aa9 100644
--- a/src/cl_device_data.h
+++ b/src/cl_device_data.h
@@ -155,7 +155,6 @@
 #define PCI_CHIP_HASWELL_CRW_E2      0x0D1E /* CRW GT2 */
 #define PCI_CHIP_HASWELL_CRW_E3      0x0D2E /* CRW GT3 */
 
-
 #define IS_HASWELL(devid) (  \
 	(devid) == PCI_CHIP_HASWELL_D1 || (devid) == PCI_CHIP_HASWELL_D2 || \
 	(devid) == PCI_CHIP_HASWELL_D3 || (devid) == PCI_CHIP_HASWELL_S1 || \
@@ -190,5 +189,46 @@
 
 #define IS_GEN75(devid)  IS_HASWELL(devid)
 
+/* BRW */
+#define PCI_CHIP_BROADWLL_M_GT1       0x1602 /* Intel(R) Broadwell Mobile - Halo (EDRAM) - GT1 */
+#define PCI_CHIP_BROADWLL_D_GT1       0x1606 /* Intel(R) Broadwell U-Processor - GT1 */
+#define PCI_CHIP_BROADWLL_S_GT1       0x160A /* Intel(R) Broadwell Server - GT1 */
+#define PCI_CHIP_BROADWLL_W_GT1       0x160D /* Intel(R) Broadwell Workstation - GT1 */
+#define PCI_CHIP_BROADWLL_U_GT1       0x160E /* Intel(R) Broadwell ULX - GT1 */
+#define PCI_CHIP_BROADWLL_M_GT2       0x1612 /* Intel(R) Broadwell Mobile - Halo (EDRAM) - GT2 */
+#define PCI_CHIP_BROADWLL_D_GT2       0x1616 /* Intel(R) Broadwell U-Processor - GT2 */
+#define PCI_CHIP_BROADWLL_S_GT2       0x161A /* Intel(R) Broadwell Server - GT2 */
+#define PCI_CHIP_BROADWLL_W_GT2       0x161D /* Intel(R) Broadwell Workstation - GT2 */
+#define PCI_CHIP_BROADWLL_U_GT2       0x161E /* Intel(R) Broadwell ULX - GT2 */
+#define PCI_CHIP_BROADWLL_M_GT3       0x1622 /* Intel(R) Broadwell Mobile - Halo (EDRAM) - GT3 */
+#define PCI_CHIP_BROADWLL_D_GT3       0x1626 /* Intel(R) Broadwell U-Processor - GT3 */
+#define PCI_CHIP_BROADWLL_S_GT3       0x162A /* Intel(R) Broadwell Server - GT3 */
+#define PCI_CHIP_BROADWLL_W_GT3       0x162D /* Intel(R) Broadwell Workstation - GT3 */
+#define PCI_CHIP_BROADWLL_U_GT3       0x162E /* Intel(R) Broadwell ULX - GT3 */
+
+#define IS_BRW_GT1(devid)               \
+  (devid == PCI_CHIP_BROADWLL_M_GT1 ||   \
+   devid == PCI_CHIP_BROADWLL_D_GT1 || \
+   devid == PCI_CHIP_BROADWLL_S_GT1 || \
+   devid == PCI_CHIP_BROADWLL_W_GT1 || \
+   devid == PCI_CHIP_BROADWLL_U_GT1)
+
+#define IS_BRW_GT2(devid)               \
+  (devid == PCI_CHIP_BROADWLL_M_GT2 ||   \
+   devid == PCI_CHIP_BROADWLL_D_GT2 || \
+   devid == PCI_CHIP_BROADWLL_S_GT2 || \
+   devid == PCI_CHIP_BROADWLL_W_GT2 || \
+   devid == PCI_CHIP_BROADWLL_U_GT2)
+
+#define IS_BRW_GT3(devid)               \
+  (devid == PCI_CHIP_BROADWLL_M_GT3 ||   \
+   devid == PCI_CHIP_BROADWLL_D_GT3 || \
+   devid == PCI_CHIP_BROADWLL_S_GT3 || \
+   devid == PCI_CHIP_BROADWLL_W_GT3 || \
+   devid == PCI_CHIP_BROADWLL_U_GT3)
+
+#define IS_BROADWELL(devid) (IS_BRW_GT1(devid) || IS_BRW_GT2(devid) || IS_BRW_GT3(devid))
+#define IS_GEN8(devid)      IS_BROADWELL(devid)
+
 #endif /* __CL_DEVICE_DATA_H__ */
 
diff --git a/src/cl_device_id.c b/src/cl_device_id.c
index 1ce53805..9e63e813 100644
--- a/src/cl_device_id.c
+++ b/src/cl_device_id.c
@@ -97,6 +97,38 @@ static struct _cl_device_id intel_hsw_gt3_device = {
 #include "cl_gen75_device.h"
 };
 
+/* XXX we clone IVB for HSW now */
+static struct _cl_device_id intel_brw_gt1_device = {
+  INIT_ICD(dispatch)
+  .max_compute_unit = 12,
+  .max_thread_per_unit = 7,
+  .max_work_item_sizes = {1024, 1024, 1024},
+  .max_work_group_size = 1024,
+  .max_clock_frequency = 1000,
+#include "cl_gen75_device.h"
+};
+
+static struct _cl_device_id intel_brw_gt2_device = {
+  INIT_ICD(dispatch)
+  .max_compute_unit = 24,
+  .max_thread_per_unit = 7,
+  .max_work_item_sizes = {1024, 1024, 1024},
+  .max_work_group_size = 1024,
+  .max_clock_frequency = 1000,
+#include "cl_gen75_device.h"
+};
+
+static struct _cl_device_id intel_brw_gt3_device = {
+  INIT_ICD(dispatch)
+  .max_compute_unit = 48,
+  .max_thread_per_unit = 7,
+  .max_work_item_sizes = {1024, 1024, 1024},
+  .max_work_group_size = 1024,
+  .max_clock_frequency = 1000,
+#include "cl_gen75_device.h"
+};
+
+
 LOCAL cl_device_id
 cl_get_gt_device(void)
 {
@@ -286,6 +318,54 @@ baytrail_t_device_break:
       ret = &intel_baytrail_t_device;
       break;
 
+    case PCI_CHIP_BROADWLL_M_GT1:
+      DECL_INFO_STRING(brw_gt1_break, intel_brw_gt1_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_D_GT1:
+      DECL_INFO_STRING(brw_gt1_break, intel_brw_gt1_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_S_GT1:
+      DECL_INFO_STRING(brw_gt1_break, intel_brw_gt1_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_W_GT1:
+      DECL_INFO_STRING(brw_gt1_break, intel_brw_gt1_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_U_GT1:
+      DECL_INFO_STRING(brw_gt1_break, intel_brw_gt1_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+brw_gt1_break:
+      intel_brw_gt1_device.vendor_id = device_id;
+      intel_brw_gt1_device.platform = intel_platform;
+      ret = &intel_brw_gt1_device;
+      break;
+
+    case PCI_CHIP_BROADWLL_M_GT2:
+      DECL_INFO_STRING(brw_gt2_break, intel_brw_gt2_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_D_GT2:
+      DECL_INFO_STRING(brw_gt2_break, intel_brw_gt2_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_S_GT2:
+      DECL_INFO_STRING(brw_gt2_break, intel_brw_gt2_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_W_GT2:
+      DECL_INFO_STRING(brw_gt2_break, intel_brw_gt2_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_U_GT2:
+      DECL_INFO_STRING(brw_gt2_break, intel_brw_gt2_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+brw_gt2_break:
+      intel_brw_gt2_device.vendor_id = device_id;
+      intel_brw_gt2_device.platform = intel_platform;
+      ret = &intel_brw_gt2_device;
+      break;
+
+    case PCI_CHIP_BROADWLL_M_GT3:
+      DECL_INFO_STRING(brw_gt3_break, intel_brw_gt3_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_D_GT3:
+      DECL_INFO_STRING(brw_gt3_break, intel_brw_gt3_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_S_GT3:
+      DECL_INFO_STRING(brw_gt3_break, intel_brw_gt3_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_W_GT3:
+      DECL_INFO_STRING(brw_gt3_break, intel_brw_gt3_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+    case PCI_CHIP_BROADWLL_U_GT3:
+      DECL_INFO_STRING(brw_gt3_break, intel_brw_gt3_device, name, "Intel(R) HD Graphics IvyBridge GT1");
+brw_gt3_break:
+      intel_brw_gt3_device.vendor_id = device_id;
+      intel_brw_gt3_device.platform = intel_platform;
+      ret = &intel_brw_gt3_device;
+      break;
+
     case PCI_CHIP_SANDYBRIDGE_BRIDGE:
     case PCI_CHIP_SANDYBRIDGE_GT1:
     case PCI_CHIP_SANDYBRIDGE_GT2:
@@ -380,7 +460,10 @@ cl_get_device_info(cl_device_id     device,
                device != &intel_baytrail_t_device &&
                device != &intel_hsw_gt1_device &&
                device != &intel_hsw_gt2_device &&
-               device != &intel_hsw_gt3_device
+               device != &intel_hsw_gt3_device &&
+               device != &intel_brw_gt1_device &&
+               device != &intel_brw_gt2_device &&
+               device != &intel_brw_gt3_device
                ))
     return CL_INVALID_DEVICE;
 
@@ -482,7 +565,10 @@ cl_device_get_version(cl_device_id device, cl_int *ver)
                device != &intel_baytrail_t_device &&
                device != &intel_hsw_gt1_device &&
                device != &intel_hsw_gt2_device &&
-               device != &intel_hsw_gt3_device))
+               device != &intel_hsw_gt3_device &&
+               device != &intel_brw_gt1_device &&
+               device != &intel_brw_gt2_device &&
+               device != &intel_brw_gt3_device))
     return CL_INVALID_DEVICE;
   if (ver == NULL)
     return CL_SUCCESS;
@@ -493,6 +579,9 @@ cl_device_get_version(cl_device_id device, cl_int *ver)
   } else if (device == &intel_hsw_gt1_device || device == &intel_hsw_gt2_device
         || device == &intel_hsw_gt3_device) {
     *ver = 75;
+  } else if (device == &intel_brw_gt1_device || device == &intel_brw_gt2_device
+        || device == &intel_brw_gt3_device) {
+    *ver = 8;
   } else
     return CL_INVALID_VALUE;
 
@@ -565,7 +654,10 @@ cl_get_kernel_workgroup_info(cl_kernel kernel,
                device != &intel_baytrail_t_device &&
                device != &intel_hsw_gt1_device &&
                device != &intel_hsw_gt2_device &&
-               device != &intel_hsw_gt3_device))
+               device != &intel_hsw_gt3_device &&
+               device != &intel_brw_gt1_device &&
+               device != &intel_brw_gt2_device &&
+               device != &intel_brw_gt3_device))
     return CL_INVALID_DEVICE;
 
   CHECK_KERNEL(kernel);