Merge branch 'master' into xf86-video-intel-2.5-branch

10 files changed, 87 insertions, 92 deletions

diff --git a/man/intel.man b/man/intel.man
index 115b35ac..15ab2345 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -135,27 +135,12 @@ Disable or enable XVideo support.
 Default: XVideo is enabled for configurations where it is supported.
 .TP
 .BI "Option \*qLegacy3D\*q \*q" boolean \*q
-Enable support for the legacy i915_dri.so 3D driver.
-This will, among other things, make the 2D driver tell libGL to
-load the 3D driver i915_dri.so instead of the newer i915tex_dri.so.
-This option is only used for chipsets in the range i830-i945.
-Default for i830-i945 series: Enabled.
-Default for i810: The option is not used.
-Default for i965: The option is always true.
-.TP
-.BI "Option \*qAperTexSize\*q \*q" integer \*q
-Give the size in kiB of the AGP aperture area that is reserved for the
-DRM memory manager present in i915 drm from version 1.7.0 and upwards,
-and that is used with the 3D driver in Mesa from version 6.5.2 and
-upwards. If the size is set too high to make room for pre-allocated
-VideoRam, the driver will try to reduce it automatically. If you use only
-older Mesa or DRM versions, you may set this value to zero, and
-activate the legacy texture pool (see 
-.B "Option \*qLegacy3D\*q"
-). If you run 3D programs with large texture memory requirements, you might
-gain some performance by increasing this value.
-Default: 32768.
-.TP
+Enable support for the non-GEM mode of the 3D driver on i830 and newer.
+This will allocate a large static area for older Mesa to use for its texture
+pool.  On systems with a working GEM environment, this can be disabled to
+increase the memory pool available to other graphics tasks.
+Default for i830 and newer: Enabled.
+Default for i810: this option is not used.
 .BI "Option \*qPageFlip\*q \*q" boolean \*q
 Enable support for page flipping. This should improve 3D performance at the
 potential cost of worse performance with mixed 2D/3D. Also note that this gives
diff --git a/src/i830_accel.c b/src/i830_accel.c
index 2743445f..fe76fa0c 100644
--- a/src/i830_accel.c
+++ b/src/i830_accel.c
@@ -192,7 +192,7 @@ I830Sync(ScrnInfoPtr pScrn)
 
    I830EmitFlush(pScrn);
 
-   intel_batch_flush(pScrn);
+   intel_batch_flush(pScrn, TRUE);
 
    if (pI830->directRenderingEnabled) {
        struct drm_i915_irq_emit emit;
@@ -237,9 +237,8 @@ I830EmitFlush(ScrnInfoPtr pScrn)
       flags = 0;
 
    {
-       BEGIN_BATCH(2);
+       BEGIN_BATCH(1);
        OUT_BATCH(MI_FLUSH | flags);
-       OUT_BATCH(MI_NOOP);		/* pad to quadword */
        ADVANCE_BATCH();
    }
 }
diff --git a/src/i830_batchbuffer.c b/src/i830_batchbuffer.c
index cd8f687f..a770616c 100644
--- a/src/i830_batchbuffer.c
+++ b/src/i830_batchbuffer.c
@@ -156,7 +156,7 @@ intel_batch_teardown(ScrnInfoPtr pScrn)
 }
 
 void
-intel_batch_flush(ScrnInfoPtr pScrn)
+intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
 {
     I830Ptr pI830 = I830PTR(pScrn);
     int ret;
@@ -164,6 +164,17 @@ intel_batch_flush(ScrnInfoPtr pScrn)
     if (pI830->batch_used == 0)
 	return;
 
+    /* If we're not using GEM, then emit a flush after each batch buffer */
+    if (pI830->memory_manager == NULL && !flushed) {
+	int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
+
+	if (IS_I965G(pI830))
+	    flags = 0;
+
+	*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_FLUSH | flags;
+	pI830->batch_used += 4;
+    }
+	
     /* Emit a padding dword if we aren't going to be quad-word aligned. */
     if ((pI830->batch_used & 4) == 0) {
 	*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_NOOP;
@@ -188,5 +199,6 @@ intel_batch_flush(ScrnInfoPtr pScrn)
      * blockhandler.  We could set this less often, but it's probably not worth
      * the work.
      */
-    pI830->need_mi_flush = TRUE;
+    if (pI830->memory_manager != NULL)
+	pI830->need_mi_flush = TRUE;
 }
diff --git a/src/i830_batchbuffer.h b/src/i830_batchbuffer.h
index 3c7a69be..05114936 100644
--- a/src/i830_batchbuffer.h
+++ b/src/i830_batchbuffer.h
@@ -34,7 +34,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 void intel_batch_init(ScrnInfoPtr pScrn);
 void intel_batch_teardown(ScrnInfoPtr pScrn);
-void intel_batch_flush(ScrnInfoPtr pScrn);
+void intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed);
 
 static inline int
 intel_batch_space(I830Ptr pI830)
@@ -47,7 +47,7 @@ intel_batch_require_space(ScrnInfoPtr pScrn, I830Ptr pI830, GLuint sz)
 {
     assert(sz < pI830->batch_bo->size - 8);
     if (intel_batch_space(pI830) < sz)
-	intel_batch_flush(pScrn);
+	intel_batch_flush(pScrn, FALSE);
 }
 
 static inline void
@@ -119,8 +119,8 @@ do {									\
     if (pI830->batch_emitting != 0)					\
 	FatalError("%s: BEGIN_BATCH called without closing "		\
 		   "ADVANCE_BATCH\n", __FUNCTION__);			\
+    intel_batch_require_space(pScrn, pI830, (n) * 4);			\
     pI830->batch_emitting = (n) * 4;					\
-    intel_batch_require_space(pScrn, pI830, pI830->batch_emitting);	\
     pI830->batch_emit_start = pI830->batch_used;			\
 } while (0)
 
@@ -140,7 +140,7 @@ do {									\
 		   pI830->batch_emitting);				\
     if ((pI830->batch_emitting > 8) && (I810_DEBUG & DEBUG_ALWAYS_SYNC)) { \
 	/* Note: not actually syncing, just flushing each batch. */	\
-	intel_batch_flush(pScrn);					\
+	intel_batch_flush(pScrn, FALSE);					\
     }									\
     pI830->batch_emitting = 0;						\
 } while (0)
diff --git a/src/i830_common.h b/src/i830_common.h
index f3a7ea01..eeb2ed76 100644
--- a/src/i830_common.h
+++ b/src/i830_common.h
@@ -124,14 +124,14 @@ typedef struct {
         unsigned int rotated_tiled;
         unsigned int rotated2_tiled;
 
-	int planeA_x;
-	int planeA_y;
-	int planeA_w;
-	int planeA_h;
-	int planeB_x;
-	int planeB_y;
-	int planeB_w;
-	int planeB_h;
+	int pipeA_x;
+	int pipeA_y;
+	int pipeA_w;
+	int pipeA_h;
+	int pipeB_x;
+	int pipeB_y;
+	int pipeB_w;
+	int pipeB_h;
 
 	/* Triple buffering */
 	drm_handle_t third_handle;
diff --git a/src/i830_display.c b/src/i830_display.c
index 0632f3a3..341def92 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -428,14 +428,14 @@ i830PipeSetBase(xf86CrtcPtr crtc, int x, int y)
 	if (!sPriv)
 	    return;
 
-	switch (plane) {
+	switch (pipe) {
 	case 0:
-	    sPriv->planeA_x = x;
-	    sPriv->planeA_y = y;
+	    sPriv->pipeA_x = x;
+	    sPriv->pipeA_y = y;
 	    break;
 	case 1:
-	    sPriv->planeB_x = x;
-	    sPriv->planeB_y = y;
+	    sPriv->pipeB_x = x;
+	    sPriv->pipeB_y = y;
 	    break;
 	default:
 	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -756,7 +756,7 @@ static void i830_modeset_ctl(xf86CrtcPtr crtc, int pre)
     if (!pI830->directRenderingEnabled)
       return;
 
-    modeset.crtc = intel_crtc->plane;
+    modeset.crtc = intel_crtc->pipe;
 
     /*
      * DPMS will be called many times (especially off), but we only
@@ -921,14 +921,14 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
 	if (!sPriv)
 	    return;
 
-	switch (plane) {
+	switch (pipe) {
 	case 0:
-	    sPriv->planeA_w = enabled ? crtc->mode.HDisplay : 0;
-	    sPriv->planeA_h = enabled ? crtc->mode.VDisplay : 0;
+	    sPriv->pipeA_w = enabled ? crtc->mode.HDisplay : 0;
+	    sPriv->pipeA_h = enabled ? crtc->mode.VDisplay : 0;
 	    break;
 	case 1:
-	    sPriv->planeB_w = enabled ? crtc->mode.HDisplay : 0;
-	    sPriv->planeB_h = enabled ? crtc->mode.VDisplay : 0;
+	    sPriv->pipeB_w = enabled ? crtc->mode.HDisplay : 0;
+	    sPriv->pipeB_h = enabled ? crtc->mode.VDisplay : 0;
 	    break;
 	default:
 	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 16f37357..c60ee246 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -1197,7 +1197,6 @@ I830DRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 index)
    int nbox;
    int buffer, first_buffer, last_buffer;
 
-   return;
    if (I810_DEBUG & DEBUG_VERBOSE_DRI)
       ErrorF("I830DRIInitBuffers\n");
 
@@ -1506,14 +1505,14 @@ I830DRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num)
       unsigned numvisible[2] = { 0, 0 };
       int i, j;
 
-      crtcBox[0].x1 = sPriv->planeA_x;
-      crtcBox[0].y1 = sPriv->planeA_y;
-      crtcBox[0].x2 = crtcBox[0].x1 + sPriv->planeA_w;
-      crtcBox[0].y2 = crtcBox[0].y1 + sPriv->planeA_h;
-      crtcBox[1].x1 = sPriv->planeB_x;
-      crtcBox[1].y1 = sPriv->planeB_y;
-      crtcBox[1].x2 = crtcBox[1].x1 + sPriv->planeB_w;
-      crtcBox[1].y2 = crtcBox[1].y1 + sPriv->planeB_h;
+      crtcBox[0].x1 = sPriv->pipeA_x;
+      crtcBox[0].y1 = sPriv->pipeA_y;
+      crtcBox[0].x2 = crtcBox[0].x1 + sPriv->pipeA_w;
+      crtcBox[0].y2 = crtcBox[0].y1 + sPriv->pipeA_h;
+      crtcBox[1].x1 = sPriv->pipeB_x;
+      crtcBox[1].y1 = sPriv->pipeB_y;
+      crtcBox[1].x2 = crtcBox[1].x1 + sPriv->pipeB_w;
+      crtcBox[1].y2 = crtcBox[1].y1 + sPriv->pipeB_h;
 
       for (i = 0; i < 2; i++) {
 	 for (j = 0; j < num; j++) {
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 2e503afd..25bcb475 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -306,9 +306,7 @@ typedef enum {
    OPTION_LVDS24BITMODE,
    OPTION_FBC,
    OPTION_TILING,
-#ifdef XF86DRI
-   OPTION_INTELTEXPOOL,
-#endif
+   OPTION_LEGACY3D,
    OPTION_LVDSFIXEDMODE,
    OPTION_TRIPLEBUFFER,
    OPTION_FORCEENABLEPIPEA,
@@ -334,7 +332,7 @@ static OptionInfoRec I830Options[] = {
    {OPTION_FBC,		"FramebufferCompression", OPTV_BOOLEAN, {0}, TRUE},
    {OPTION_TILING,	"Tiling",	OPTV_BOOLEAN,	{0},	TRUE},
 #ifdef XF86DRI
-   {OPTION_INTELTEXPOOL,"Legacy3D",     OPTV_BOOLEAN,	{0},	FALSE},
+   {OPTION_LEGACY3D,	"Legacy3D",     OPTV_BOOLEAN,	{0},	FALSE},
 #endif
    {OPTION_LVDSFIXEDMODE, "LVDSFixedMode", OPTV_BOOLEAN,	{0},	FALSE},
    {OPTION_TRIPLEBUFFER, "TripleBuffer", OPTV_BOOLEAN,	{0},	FALSE},
@@ -1567,22 +1565,8 @@ I830AccelMethodInit(ScrnInfoPtr pScrn)
 	}
 
 	if (!pI830->directRenderingDisabled) {
-	    pI830->allocate_classic_textures = TRUE;
-
-	    from = X_PROBED;
-
-#ifdef XF86DRI_MM
-	    if (!IS_I965G(pI830)) {
-		Bool tmp;
-
-		if (xf86GetOptValBool(pI830->Options,
-				      OPTION_INTELTEXPOOL, &tmp)) {
-		    from = X_CONFIG;
-		    if (!tmp)
-			pI830->allocate_classic_textures = FALSE;
-		}
-	    }
-#endif /* XF86DRI_MM */
+	   pI830->allocate_classic_textures =
+	      xf86ReturnOptValBool(pI830->Options, OPTION_LEGACY3D, TRUE);
 	}
     }
 #endif /* XF86DRI */
@@ -2674,17 +2658,21 @@ I830BlockHandler(int i,
     pScreen->BlockHandler = I830BlockHandler;
 
     if (pScrn->vtSema && pI830->accel != ACCEL_NONE) {
+       Bool flushed = FALSE;
        /* Emit a flush of the rendering cache, or on the 965 and beyond
 	* rendering results may not hit the framebuffer until significantly
 	* later.
 	*/
        if (pI830->accel != ACCEL_NONE && (pI830->need_mi_flush || pI830->batch_used))
+       {
+	  flushed = TRUE;
 	  I830EmitFlush(pScrn);
+       }
 
        /* Flush the batch, so that any rendering is executed in a timely
 	* fashion.
 	*/
-       intel_batch_flush(pScrn);
+       intel_batch_flush(pScrn, flushed);
 #ifdef XF86DRI
        if (pI830->memory_manager)
 	 drmCommandNone(pI830->drmSubFD, DRM_I915_GEM_THROTTLE);
diff --git a/src/i830_exa.c b/src/i830_exa.c
index cba9622b..e1cf24e7 100644
--- a/src/i830_exa.c
+++ b/src/i830_exa.c
@@ -252,7 +252,7 @@ I830EXADoneSolid(PixmapPtr pPixmap)
     ScrnInfoPtr pScrn = xf86Screens[pPixmap->drawable.pScreen->myNum];
 
 #if ALWAYS_FLUSH
-    intel_batch_flush(pScrn);
+    intel_batch_flush(pScrn, FALSE);
 #endif
 #if ALWAYS_SYNC
     I830Sync(pScrn);
@@ -353,7 +353,7 @@ I830EXADoneCopy(PixmapPtr pDstPixmap)
     ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
 
 #if ALWAYS_FLUSH
-    intel_batch_flush(pScrn);
+    intel_batch_flush(pScrn, FALSE);
 #endif
 #if ALWAYS_SYNC
     I830Sync(pScrn);
@@ -374,7 +374,7 @@ i830_done_composite(PixmapPtr pDst)
     ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
 
 #if ALWAYS_FLUSH
-    intel_batch_flush(pScrn);
+    intel_batch_flush(pScrn, FALSE);
 #endif
 #if ALWAYS_SYNC
     I830Sync(pScrn);
@@ -530,7 +530,7 @@ static Bool I830EXAPrepareAccess(PixmapPtr pPix, int index)
 	return TRUE;
     }
 
-    intel_batch_flush(scrn);
+    intel_batch_flush(scrn, FALSE);
     if (i830->need_sync) {
 	I830Sync(scrn);
 	i830->need_sync = FALSE;
@@ -771,7 +771,7 @@ i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access)
 	ScrnInfoPtr scrn = xf86Screens[screen->myNum];
 	I830Ptr i830 = I830PTR(scrn);
 	
-	intel_batch_flush(scrn);
+	intel_batch_flush(scrn, FALSE);
 	if (i830->need_sync) {
 	    I830Sync(scrn);
 	    i830->need_sync = FALSE;
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 505564f5..caae1350 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -393,6 +393,7 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
     int dri_major, dri_minor, dri_patch;
     struct drm_i915_getparam gp;
     int has_gem;
+    int has_dri;
 #endif
 
     start = xcalloc(1, sizeof(*start));
@@ -431,21 +432,32 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
     pI830->memory_list = start;
 
 #ifdef XF86DRI
-    DRIQueryVersion(&dri_major, &dri_minor, &dri_patch);
-
-    has_gem = 0;
-    gp.param = I915_PARAM_HAS_GEM;
-    gp.value = &has_gem;
+    has_gem = FALSE;
+    has_dri = FALSE;
+    
+    if (pI830->directRenderingEnabled &&
+	xf86LoaderCheckSymbol ("DRIQueryVersion"))
+    {
+	DRIQueryVersion(&dri_major, &dri_minor, &dri_patch);
+	has_dri = TRUE;
+    }
 
-    (void)drmCommandWriteRead(pI830->drmSubFD, DRM_I915_GETPARAM,
-			      &gp, sizeof(gp));
+    if (pI830->directRenderingEnabled)
+    {
+	has_gem = FALSE;
+	gp.param = I915_PARAM_HAS_GEM;
+	gp.value = &has_gem;
+    
+	(void)drmCommandWriteRead(pI830->drmSubFD, DRM_I915_GETPARAM,
+				  &gp, sizeof(gp));
+    }
 
     /* Now that we have our manager set up, initialize the kernel MM if
      * possible, covering almost all of the aperture.  We need libdri interface
      * 5.4 or newer so we can rely on the lock being held after DRIScreenInit,
      * rather than after DRIFinishScreenInit.
      */
-    if (pI830->directRenderingEnabled && has_gem &&
+    if (pI830->directRenderingEnabled && has_gem && has_dri &&
 	(dri_major > 5 || (dri_major == 5 && dri_minor >= 4)))
     {
 	int mmsize;