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2013-03-17target-mips: fix rndrashift_short_acc and code for EXTR_ instructionsPetar Jovanovic1-14/+9
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber4-3/+7
2013-03-12cpu: Pass CPUState to cpu_interrupt()Andreas Färber1-4/+4
2013-03-12exec: Pass CPUState to cpu_reset_interrupt()Andreas Färber1-3/+2
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber3-7/+11
2013-03-05mips64-linux-user: Enable 64-bit address mode and fpuRichard Henderson1-0/+12
2013-03-05mips-linux-user: Save and restore fpu and dsp from sigcontextRichard Henderson2-3/+16
2013-03-05target-mips: Fix accumulator selection for MIPS16 and microMIPSRichard Sandiford1-84/+64
2013-03-04target-mips: fix DSP overflow macro and affected routinesPetar Jovanovic1-42/+48
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber1-0/+1
2013-02-23target-mips: fix for sign-issue in MULQ_W helperPetar Jovanovic1-1/+1
2013-02-23target-mips: fix for incorrect multiplication with MULQ_S.PHPetar Jovanovic1-1/+1
2013-02-23target-mips: Use mul[us]2 in [D]MULT[U] insnsRichard Henderson3-42/+20
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber1-0/+2
2013-02-16target-mips: Move TCG initialization to MIPSCPU initfnAndreas Färber3-2/+6
2013-02-16target-mips: Introduce QOM realizefn for MIPSCPUAndreas Färber3-2/+20
2013-01-31target-mips: enable access to DSP ASE if implementedPetar Jovanovic1-4/+2
2013-01-31target-mips: Unfuse {,N}M{ADD,SUB}.fmtRichard Sandiford1-8/+17
2013-01-31target-mips: Sign-extend the result of LWRRichard Sandiford1-0/+1
2013-01-31target-mips: Fix signedness of loads in MIPS16 RESTOREsRichard Sandiford1-1/+1
2013-01-31target-mips: implement DSP (d)append sub-class with TCGAurelien Jarno3-126/+87
2013-01-31target-mips: use DSP unions for reduction add instructionsAurelien Jarno1-16/+14
2013-01-31target-mips: use DSP unions for unary DSP operatorsAurelien Jarno1-82/+42
2013-01-31target-mips: use DSP unions for binary DSP operatorsAurelien Jarno1-268/+116
2013-01-31target-mips: add unions to access DSP elementsAurelien Jarno1-0/+22
2013-01-31target-mips: generate a reserved instruction exception on CPU without DSPAurelien Jarno1-2/+10
2013-01-31target-mips: copy insn_flags in DisasContextAurelien Jarno1-381/+381
2013-01-31target-mips: fix DSP loads with rd = 0Aurelien Jarno1-5/+0
2013-01-15exec: Return CPUState from qemu_get_cpu()Andreas Färber1-3/+8
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber2-10/+15
2013-01-15target-mips: Clean up mips_cpu_map_tc() documentationAndreas Färber1-5/+9
2013-01-15cpu: Move nr_{cores,threads} fields to CPUStateAndreas Färber1-3/+5
2013-01-08target-mips: Fix helper and tests for dot/cross-dot product instructionsPetar Jovanovic1-1/+1
2013-01-08target-mips: Replace macros by inline functionsStefan Weil1-18/+24
2013-01-08target-mips: Allow DSP access to be disabled once enabled.Eric Johnson1-1/+1
2013-01-01target-mips: Use EXCP_SC rather than a magic number陳韋任 (Wei-Ren Chen)1-3/+2
2013-01-01target-mips: Make repl_ph to sign extend to target-longJovanovic, Petar1-1/+2
2013-01-01Fix my email addressDongxue Zhang1-1/+1
2013-01-01target-mips: Remove semicolon from macro definitionStefan Weil1-1/+1
2013-01-01target-mips: Fix for helpers for EXTR_* instructionsPetar Jovanovic1-35/+10
2013-01-01target-mips: Fix incorrect reads and writes to DSPControl registerPetar Jovanovic1-0/+8
2012-12-19fpu: move public header file to include/fpuPaolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
2012-12-19qom: move include files to include/qom/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini4-11/+11
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-16exec: refactor cpu_restore_stateBlue Swirl1-7/+1
2012-12-08Merge branch 'master' of git.qemu-project.org:/pub/git/qemuBlue Swirl1-9/+10
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
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