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authorRichard Sandiford <rdsandiford@googlemail.com>2011-11-26 03:37:07 +0000
committerBlue Swirl <blauwirbel@gmail.com>2012-05-19 15:51:44 +0000
commitd7f66b52dee3dd7423a28c0ceb600aec388859cb (patch)
treebff8fc00c7de231033cd174ffb4e56d31c36139f /target-mips
parent77a8f1a5125457d845fac6aa0c2e1e2681d94f07 (diff)
mips: Fix BC1ANY[24]F instructions
There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is. Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f5297b039..0c563eedf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -6099,7 +6099,7 @@ static void gen_compute_branch1 (CPUMIPSState *env, DisasContext *ctx, uint32_t
TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
- tcg_gen_nor_i32(t0, t0, t1);
+ tcg_gen_nand_i32(t0, t0, t1);
tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1);
tcg_gen_extu_i32_tl(bcond, t0);
@@ -6123,11 +6123,11 @@ static void gen_compute_branch1 (CPUMIPSState *env, DisasContext *ctx, uint32_t
TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
- tcg_gen_or_i32(t0, t0, t1);
+ tcg_gen_and_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
- tcg_gen_or_i32(t0, t0, t1);
+ tcg_gen_and_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
- tcg_gen_nor_i32(t0, t0, t1);
+ tcg_gen_nand_i32(t0, t0, t1);
tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1);
tcg_gen_extu_i32_tl(bcond, t0);