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authorNathan Froyd <froydnj@codesourcery.com>2010-02-20 10:24:07 -0800
committerAurelien Jarno <aurelien@aurel32.net>2010-02-23 19:47:25 +0100
commit3399e30f562df9f67ccad4d4f4367d31120f996f (patch)
tree0d61db3d902d169a93e127723ffd7e4dcd881d7b /target-mips
parentc2c65dab45bc640dc7a3d1fb259472b029bb420f (diff)
target-mips: fix ROTR and DROTR by zero
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index eb46b42ed..ba660ab8a 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1475,6 +1475,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
tcg_gen_rotri_i32(t1, t1, uimm);
tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
tcg_temp_free_i32(t1);
+ } else {
+ tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
}
opn = "rotr";
break;
@@ -1494,6 +1496,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
case OPC_DROTR:
if (uimm != 0) {
tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
+ } else {
+ tcg_gen_mov_tl(cpu_gpr[rt], t0);
}
opn = "drotr";
break;