MIPS FPU support (Marius Goeger)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1964 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 9 insertions, 3 deletions

diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index 6d28e9cd0..317f6a47f 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -24,6 +24,12 @@ enum {
 /* Uses MIPS R4Kc TLB model */
 #define MIPS_USES_R4K_TLB
 #define MIPS_TLB_NB 16
+/* basic FPU register support */
+#define MIPS_USES_FPU 1
+/* Define a implementation number of 1.
+ * Define a major version 1, minor version 0.
+ */
+#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
 /* Have config1, runs in big-endian mode, uses TLB */
 #define MIPS_CONFIG0                                            \
 ((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) |  \
@@ -31,14 +37,14 @@ enum {
 /* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
  * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
  * no performance counters, watch registers present, no code compression,
- * EJTAG present, no FPU
+ * EJTAG present, FPU enable bit depending on MIPS_USES_FPU
  */
 #define MIPS_CONFIG1                                            \
 ((15 << CP0C1_MMU) |                                            \
  (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \
  (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \
  (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) |          \
- (1 << CP0C1_EP) | (0 << CP0C1_FP))
+ (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP))
 #elif defined (MIPS_CPU == MIPS_R4Kp)
 /* 32 bits target */
 #define TARGET_LONG_BITS 32
@@ -52,7 +58,7 @@ enum {
 #error "MIPS CPU not defined"
 /* Remainder for other flags */
 //#define TARGET_MIPS64
-//define MIPS_USES_FPU
+//#define MIPS_USES_FPU
 #endif
 
 #endif /* !defined (__QEMU_MIPS_DEFS_H__) */