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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2005-04-23 18:18:54 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2005-04-23 18:18:54 +0000
commitda9b266bb8491fd41badfff8ae1772007602dcca (patch)
treea03a33b4b87c42a3dd86d4aab3dbee53f9fada9d /hw/pci.c
parentdccfafc4e1325dbf90d8ee7b2bc56e6e02eaf4b5 (diff)
PREP machines have two IO mappings.
This patch adds support for non-contiguous IO map, which is used by OS/2. It also adds the missing legacy IO ports for the PREP PCI bridge and changes CPU PVR from 74x/75x to 604 to make OS/2 happy. (Jocelyn Mayer) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1381 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pci.c')
-rw-r--r--hw/pci.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/hw/pci.c b/hw/pci.c
index 6035c890a..cb7131a6a 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -694,6 +694,16 @@ PCIBus *pci_prep_init(void)
s = pci_register_bus();
s->set_irq = prep_set_irq;
+ register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
+ register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
+
+ register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
+ register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
+ register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
+ register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
+ register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
+ register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
+
PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
PPC_PCIIO_write, s);
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);