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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-01 15:38:17 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-01 15:38:17 +0000
commit8a08f9a809f8613bb7d6c3e9389812f1b043c846 (patch)
tree6602817c7ff252385be4b2e4dced27a5f7503488 /target-sparc
parentd4218d996d2274f4136b8bd22e946bf56f050c9e (diff)
Fix Sparc shift ops (Aurelien Jarno)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2569 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/op.c19
-rw-r--r--target-sparc/translate.c7
2 files changed, 17 insertions, 9 deletions
diff --git a/target-sparc/op.c b/target-sparc/op.c
index 5c6e5391d..2c8949048 100644
--- a/target-sparc/op.c
+++ b/target-sparc/op.c
@@ -965,38 +965,43 @@ void OPPROTO op_logic_T0_cc(void)
void OPPROTO op_sll(void)
{
- T0 <<= T1;
+ T0 <<= (T1 & 0x1f);
}
#ifdef TARGET_SPARC64
+void OPPROTO op_sllx(void)
+{
+ T0 <<= (T1 & 0x3f);
+}
+
void OPPROTO op_srl(void)
{
- T0 = (T0 & 0xffffffff) >> T1;
+ T0 = (T0 & 0xffffffff) >> (T1 & 0x1f);
}
void OPPROTO op_srlx(void)
{
- T0 >>= T1;
+ T0 >>= (T1 & 0x3f);
}
void OPPROTO op_sra(void)
{
- T0 = ((int32_t) (T0 & 0xffffffff)) >> T1;
+ T0 = ((int32_t) (T0 & 0xffffffff)) >> (T1 & 0x1f);
}
void OPPROTO op_srax(void)
{
- T0 = ((int64_t) T0) >> T1;
+ T0 = ((int64_t) T0) >> (T1 & 0x3f);
}
#else
void OPPROTO op_srl(void)
{
- T0 >>= T1;
+ T0 >>= (T1 & 0x1f);
}
void OPPROTO op_sra(void)
{
- T0 = ((int32_t) T0) >> T1;
+ T0 = ((int32_t) T0) >> (T1 & 0x1f);
}
#endif
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 50d0875d1..70cf1bcdb 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1703,7 +1703,7 @@ static void disas_sparc_insn(DisasContext * dc)
}
#endif
#ifdef TARGET_SPARC64
- } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
+ } else if (xop == 0x25) { /* sll, V9 sllx */
rs1 = GET_FIELD(insn, 13, 17);
gen_movl_reg_T0(rs1);
if (IS_IMM) { /* immediate */
@@ -1713,7 +1713,10 @@ static void disas_sparc_insn(DisasContext * dc)
rs2 = GET_FIELD(insn, 27, 31);
gen_movl_reg_T1(rs2);
}
- gen_op_sll();
+ if (insn & (1 << 12))
+ gen_op_sllx();
+ else
+ gen_op_sll();
gen_movl_T0_reg(rd);
} else if (xop == 0x26) { /* srl, V9 srlx */
rs1 = GET_FIELD(insn, 13, 17);