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author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-11-12 20:40:55 +0000 |
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committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-11-12 20:40:55 +0000 |
commit | b362e5e067835d04ddde5fb1277272d4b498b970 (patch) | |
tree | 9e83ced7a49e4151d09d1965075ebe55bff6a55a /cpu-defs.h | |
parent | d08b2a28e6d71c561b84878b84e52159a63a27cc (diff) |
Speed up tlb_flush_page (Daniel Jacobowitz).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2210 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'cpu-defs.h')
-rw-r--r-- | cpu-defs.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/cpu-defs.h b/cpu-defs.h index 674c0bd3f..0b49c8991 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -80,6 +80,14 @@ typedef unsigned long ram_addr_t; #define TB_JMP_CACHE_BITS 12 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) +/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for + addresses on the same page. The top bits are the same. This allows + TLB invalidation to quickly clear a subset of the hash table. */ +#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) +#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) +#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) +#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) + #define CPU_TLB_BITS 8 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) |