radv: Use winsys HTILE info.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

6 files changed, 18 insertions, 87 deletions

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d99288a672..3796ae4b48 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -951,7 +951,7 @@ radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 	va += image->offset + image->clear_value_offset;
 	unsigned reg_offset = 0, reg_count = 0;
 
-	if (!image->htile.size || !aspects)
+	if (!image->surface.htile_size || !aspects)
 		return;
 
 	if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
@@ -990,7 +990,7 @@ radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 	uint64_t va = cmd_buffer->device->ws->buffer_get_va(image->bo);
 	va += image->offset + image->clear_value_offset;
 
-	if (!image->htile.size)
+	if (!image->surface.htile_size)
 		return;
 
 	cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
@@ -2710,8 +2710,8 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
 	cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 	                                RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
 
-	radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile.offset,
-			 image->htile.size, 0xffffffff);
+	radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->htile_offset,
+			 image->surface.htile_size, 0xffffffff);
 
 	cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
 	                                RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
@@ -2851,7 +2851,7 @@ static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
 	unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
 	unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
 
-	if (image->htile.size)
+	if (image->surface.htile_size)
 		radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
 						   dst_layout, range, pending_clears);
 
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ab04473b01..9202baaaa8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2404,7 +2404,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 		ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
 	}
 
-	if (iview->image->htile.size && !level) {
+	if (iview->image->surface.htile_size && !level) {
 		ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
 			S_028040_ALLOW_EXPCLEAR(1);
 
@@ -2427,7 +2427,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 			ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
 
 		va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
-		     iview->image->htile.offset;
+		     iview->image->htile_offset;
 		ds->db_htile_data_base = va >> 8;
 		ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
 	} else {
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index b71d8b75a0..3d650b0271 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -586,89 +586,22 @@ radv_image_alloc_dcc(struct radv_device *device,
 	image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
 }
 
-static unsigned
-radv_image_get_htile_size(struct radv_device *device,
-			  struct radv_image *image)
-{
-	unsigned cl_width, cl_height, width, height;
-	unsigned slice_elements, slice_bytes, base_align;
-	unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
-	unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
-
-	/* Overalign HTILE on P2 configs to work around GPU hangs in
-	 * piglit/depthstencil-render-miplevels 585.
-	 *
-	 * This has been confirmed to help Kabini & Stoney, where the hangs
-	 * are always reproducible. I think I have seen the test hang
-	 * on Carrizo too, though it was very rare there.
-	 */
-	if (device->physical_device->rad_info.chip_class >= CIK && num_pipes < 4)
-		num_pipes = 4;
-
-	switch (num_pipes) {
-	case 1:
-		cl_width = 32;
-		cl_height = 16;
-		break;
-	case 2:
-		cl_width = 32;
-		cl_height = 32;
-		break;
-	case 4:
-		cl_width = 64;
-		cl_height = 32;
-		break;
-	case 8:
-		cl_width = 64;
-		cl_height = 64;
-		break;
-	case 16:
-		cl_width = 128;
-		cl_height = 64;
-		break;
-	default:
-		assert(0);
-		return 0;
-	}
-
-	width = align(image->surface.npix_x, cl_width * 8);
-	height = align(image->surface.npix_y, cl_height * 8);
-
-	slice_elements = (width * height) / (8 * 8);
-	slice_bytes = slice_elements * 4;
-
-	base_align = num_pipes * pipe_interleave_bytes;
-
-	image->htile.pitch = width;
-	image->htile.height = height;
-	image->htile.xalign = cl_width * 8;
-	image->htile.yalign = cl_height * 8;
-
-	return image->array_size *
-		align(slice_bytes, base_align);
-}
-
 static void
 radv_image_alloc_htile(struct radv_device *device,
 		       struct radv_image *image)
 {
-	if (device->debug_flags & RADV_DEBUG_NO_HIZ)
-		return;
-
-	if (image->array_size > 1 || image->levels > 1)
-		return;
-
-	image->htile.size = radv_image_get_htile_size(device, image);
-
-	if (!image->htile.size)
+	if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->layers > 1 ||
+	    image->levels > 1) {
+		image->surface.htile_size = 0;
 		return;
+	}
 
-	image->htile.offset = align64(image->size, 32768);
+	image->htile_offset = align64(image->size, image->surface.htile_alignment);
 
 	/* + 8 for storing the clear values */
-	image->clear_value_offset = image->htile.offset + image->htile.size;
-	image->size = image->htile.offset + image->htile.size + 8;
-	image->alignment = align64(image->alignment, 32768);
+	image->clear_value_offset = image->htile_offset + image->surface.htile_size;
+	image->size = image->clear_value_offset + 8;
+	image->alignment = align64(image->alignment, image->surface.htile_alignment);
 }
 
 VkResult
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 67700998ca..c07775f6db 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -618,7 +618,7 @@ static bool depth_view_can_fast_clear(const struct radv_image_view *iview,
 	    clear_rect->rect.extent.width != iview->extent.width ||
 	    clear_rect->rect.extent.height != iview->extent.height)
 		return false;
-	if (iview->image->htile.size &&
+	if (iview->image->surface.htile_size &&
 	    iview->base_mip == 0 &&
 	    iview->base_layer == 0 &&
 	    radv_layout_can_expclear(iview->image, layout) &&
diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c
index 53443e9eb8..2ee27d4097 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -376,7 +376,7 @@ static void radv_process_depth_image_inplace(struct radv_cmd_buffer *cmd_buffer,
 	uint32_t height = radv_minify(image->extent.height,
 				     subresourceRange->baseMipLevel);
 
-	if (!image->htile.size)
+	if (!image->surface.htile_size)
 		return;
 	radv_meta_save_pass(&saved_pass_state, cmd_buffer);
 
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 30201a67e7..ab3e881579 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1071,14 +1071,12 @@ struct radv_image {
 	struct radeon_winsys_bo *bo;
 	VkDeviceSize offset;
 	uint32_t dcc_offset;
+	uint32_t htile_offset;
 	struct radeon_surf surface;
 
 	struct radv_fmask_info fmask;
 	struct radv_cmask_info cmask;
 	uint32_t clear_value_offset;
-
-	/* Depth buffer compression and fast clear. */
-	struct r600_htile_info htile;
 };
 
 bool radv_layout_has_htile(const struct radv_image *image,