summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
AgeCommit message (Expand)AuthorFilesLines
2016-06-28drm/i915: Tweaking PIPE_CONTROL instructionsDave Gordon1-4/+11
2016-06-28drm/i915: refactor & correct GEN6 PIPE_CONTROL codeDave Gordon1-41/+42
2016-06-28drm/i915: rationalise PIPE_CONTROL flag naming & add commentaryDave Gordon1-8/+8
2016-06-28drm/i915/gen9: add WaEnableSamplerGPGPUPreemptionSupportTim Gore1-3/+5
2016-06-28drm/i915: update ring space correctlyDave Gordon1-1/+1
2016-06-28drm/i915: Add early exit to execbuff_final() if insufficient ring spaceJohn Harrison1-0/+26
2016-06-28drm/i915: Support for 'unflushed' ring idleJohn Harrison1-2/+29
2016-06-28drm/i915: Added scheduler support to __wait_request() callsJohn Harrison1-2/+6
2016-06-28drm/i915: Disable hardware semaphores when GPU scheduler is enabledJohn Harrison1-0/+4
2016-06-28drm/i915: Interrupt driven fencesJohn Harrison1-0/+2
2016-06-28drm/i915: Delay the freeing of requests until retire timeJohn Harrison1-0/+2
2016-06-28drm/i915: Convert requests to use struct fenceJohn Harrison1-0/+1
2016-03-22drm/i915/tdr: Initialize hangcheck struct for each engineTomas Elf1-1/+6
2016-03-18drm/i915: Rename dev_priv->gtt to dev_priv->ggttJoonas Lahtinen1-1/+1
2016-03-18drm/i915/gen9: add WaClearFlowControlGpgpuContextSaveTim Gore1-0/+2
2016-03-18drm/i915: Use shorter route to dev_private where possibleTvrtko Ursulin1-1/+1
2016-03-16drm/i915: More renaming of rings to enginesTvrtko Ursulin1-8/+8
2016-03-16drm/i915: More intel_engine_cs renamingTvrtko Ursulin1-6/+6
2016-03-16drm/i915: Rename intel_engine_cs struct membersTvrtko Ursulin1-37/+37
2016-03-16drm/i915: Rename intel_engine_cs function parametersTvrtko Ursulin1-306/+312
2016-03-16drm/i915: Rename local struct intel_engine_cs variablesTvrtko Ursulin1-388/+397
2016-02-15drm/i915: Don't ERROR for an expected intel_rcs_ctx_init() interruptionChris Wilson1-2/+2
2016-02-11drm/i915: check that rpm ref is held when accessing ringbuf in stolen memDaniele Ceraolo Spurio1-0/+3
2016-01-25drm/i915/gen9: Add WaOCLCoherentLineFlushArun Siluvery1-0/+4
2016-01-25drm/i915/skl: Enable Per context Preemption granularity controlArun Siluvery1-0/+10
2016-01-25drm/i915/skl: Add GEN8_L3SQCREG4 to HW whitelistArun Siluvery1-0/+5
2016-01-25drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelistArun Siluvery1-0/+5
2016-01-25drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 to HW whitelistArun Siluvery1-0/+9
2016-01-25drm/i915/gen9: Add HDC_CHICKEN1 to HW whitelistArun Siluvery1-0/+5
2016-01-25drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelistArun Siluvery1-0/+6
2016-01-25drm/i915/gen9: Add framework to whitelist specific GPU registersArun Siluvery1-0/+17
2016-01-21drm/i915: Seal busy-ioctl uABI and prevent leaking of internal idsChris Wilson1-0/+5
2016-01-18drm/i915: Cache ringbuffer GTT VMATvrtko Ursulin1-0/+3
2016-01-15drm/i915: Make sure DC writes are coherent on flush.Francisco Jerez1-0/+2
2016-01-12drm/i915: Use MI_BATCH_BUFFER_START on 830/845Ville Syrjälä1-4/+2
2016-01-12drm/i915: Cleanup phys status page tooVille Syrjälä1-4/+20
2015-12-18drm/i915/skl: Default to noncoherent access up to F0Mika Kuoppala1-5/+5
2015-12-10drm/i915: intel_ring_initialized() must be simple and inlineDave Gordon1-26/+13
2015-12-07i915: Replace "hweight8(dev_priv->info.subslice_7eu[i]) != 1" with "!is_power...Zeng Zhaoxiu1-1/+2
2015-11-23Merge tag 'v4.4-rc2' into drm-intel-next-queuedDaniel Vetter1-0/+2
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä1-5/+8
2015-11-18drm/i915: Add functions to emit register offsets to the ringVille Syrjälä1-2/+2
2015-11-10Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds1-102/+160
2015-10-29drm/i915: make A0 wa's applied to A1Tim Gore1-2/+2
2015-10-28drm/i915: Recover all available ringbuffer space following resetChris Wilson1-3/+10
2015-10-21drm/i915: add helpers for platform specific revision id range checksJani Nikula1-32/+24
2015-10-21drm/i915/bxt: add revision id for A1 stepping and use itJani Nikula1-3/+3
2015-10-19drm/i915: Map the ringbuffer using WB on LLC machinesChris Wilson1-14/+56
2015-10-13drm/i915: Move skl/bxt gt specific workarounds to ring initMika Kuoppala1-1/+43
2015-10-13drm/i915: Flush pipecontrol post-sync writesChris Wilson1-0/+2
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 00:25:23 +0000