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2024-08-01END Remove FORCE_PROBE for BMG PCI IDsxe2Jordan Justen1-0/+0
2024-08-01intel/dev: Drop FORCE_PROBE from BMG devices (TODO: Add drm tree ref)Jordan Justen1-5/+5
2024-08-01START Remove FORCE_PROBE for BMG PCI IDsJordan Justen1-0/+0
2024-08-01END LNL WorkaroundsJordan Justen1-0/+0
2024-08-01intel/workarounds: Update json to pick up new Xe2 entriesJordan Justen1-155/+103
2024-08-01anv: implement required step for Wa_18037648410Tapani Pälli1-0/+7
2024-08-01Revert "intel/compiler: implement WA 22016140776 for LNL"Jordan Justen1-24/+0
2024-08-01blorp: implement WA 16020398787Rohan Garg1-12/+64
2024-08-01intel/compiler: implement WA 22016140776 for LNLRohan Garg1-0/+24
2024-08-01iris: implement WA 22018390030Rohan Garg1-2/+17
2024-08-01anv: implement WA 22018390030Rohan Garg1-0/+20
2024-08-01intel/compiler: Ensure that we don't emit valid EU code for WA 14017715663Rohan Garg1-0/+29
2024-08-01anv: implement WA 16020183090Rohan Garg3-0/+55
2024-08-01anv: Implement Wa_14019570772José Roberto de Souza1-0/+16
2024-08-01intel/compiler: disable mesh autostrip for WA 16020916187Rohan Garg2-0/+31
2024-08-01anv: emit WA 14018283232 when toggling bits in 3DSTATE_PS_EXTRARohan Garg1-0/+2
2024-08-01anv: send resource barrier on depth bounds change, Wa_14018283232Tapani Pälli1-0/+31
2024-08-01anv: disable fast clears for Wa_14019957668Tapani Pälli2-0/+8
2024-08-01iris: disable fast clears for Wa_14019957668Tapani Pälli2-0/+8
2024-08-01anv: implement required PSS stalls and barrier for Wa_14019039974Tapani Pälli1-0/+23
2024-08-01blorp: implement required PSS stalls for Wa_14019039974Tapani Pälli1-0/+13
2024-08-01iris: implement required PSS stall for Wa_14019039974Tapani Pälli1-0/+4
2024-08-01WIP: LNL WA 15012495196 for protected surfacesRohan Garg2-0/+8
2024-08-01START LNL WorkaroundsJordan Justen1-0/+0
2024-08-01END blorp: WA_16021232440 - Disable fastclear when height is 16k !29182Aditya Swarup1-4/+0
2024-08-01blorp: WA_16021232440 - Disable fastclear when height is 16kAditya Swarup1-0/+12
2024-08-01START blorp: WA_16021232440 - Disable fastclear when height is 16k !29182Aditya Swarup1-0/+4
2024-08-01END intel/brw: Add validation for some Xe2 register regioning restrictions !2...Caio Oliveira1-4/+0
2024-08-01fixup! intel/brw: Add validation for some Xe2 register regioning restrictionsJordan Justen1-1/+1
2024-08-01intel/brw: Add validation for some Xe2 register regioning restrictionsCaio Oliveira3-0/+150
2024-08-01START intel/brw: Add validation for some Xe2 register regioning restrictions ...Caio Oliveira1-0/+4
2024-08-01END xe2-compilerJordan Justen1-0/+0
2024-08-01intel/brw: Fix limiting Xe2 to SIMD16 when dual source blend is enabledJordan Justen1-8/+7
2024-08-01intel/brw: lower math op regions for Xe2+Rohan Garg1-2/+2
2024-08-01intel/compiler: Use 512-bit reg size for load_global_const_block on xe2Jordan Justen1-0/+3
2024-08-01SQUASH: WIP: intel/fs/xe2: Add comments/assertions for unfinished PS features.Rohan Garg1-1/+0
2024-08-01intel/brw/xe2: Add comments/assertions for unfinished PS features.Francisco Jerez1-0/+1
2024-08-01START xe2-compilerJordan Justen1-0/+0
2024-08-01END intel/brw: Xe2 TGM and UGM restrict loads of 8 or more to SIMD16 !29356Rohan Garg1-4/+0
2024-08-01intel/brw: Xe2 TGM and UGM restrict loads of 8 or more to SIMD16Rohan Garg1-4/+28
2024-08-01START intel/brw: Xe2 TGM and UGM restrict loads of 8 or more to SIMD16 !29356Rohan Garg1-0/+4
2024-08-01END Resource Barriers for LNL !26444Rohan Garg1-4/+0
2024-08-01anv: migrate CmdSetEvent2 to resource barriersRohan Garg1-24/+73
2024-08-01anv: flush caches after transitions with resource barriers on xe2+Rohan Garg1-25/+100
2024-08-01anv: Add some debugging information for resource barriersRohan Garg3-0/+92
2024-08-01anv: Migrate CmdSetEvent2 to use resource barriersRohan Garg1-9/+18
2024-08-01anv: emit a resource barrier for transitions on xe2+Rohan Garg3-23/+208
2024-08-01anv: infer signal and wait stages from masksRohan Garg1-0/+120
2024-08-01anv: convert src/dst access flags to a cache mask for resource barriersRohan Garg1-3/+207
2024-08-01anv: minor refactor when looping over memory barriers easier to readRohan Garg1-7/+8
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