summaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2022-07-21intel/dev: Determine the amount of free vram using small BAR uapismall-barJordan Justen1-2/+16
2022-07-21intel/dev: Use i915 region probed_cpu_visible_size when non-zeroJordan Justen1-1/+12
2022-07-21iris/bufmgr: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS for vram mappable ...Jordan Justen1-5/+4
2022-07-21anv: make use of the new smallbar uAPILionel Landwerlin2-5/+11
2022-07-21!UPSTREAM: drm-uapi: add i915-small-barLionel Landwerlin1-42/+140
2022-07-21anv: Prepare for new smallbar uAPILionel Landwerlin5-19/+74
2022-07-21iris/bufmgr: Add assert and TODO comment for future small BAR uapiJordan Justen1-0/+6
2022-07-21anv/allocator: Add assert and TODO comment for future small BAR uapiJordan Justen1-0/+5
2022-07-21iris: Set clear_color_unknown if the bo is not mappableJordan Justen1-9/+12
2022-07-21iris/bufmgr: Set mmap_mode to IRIS_MMAP_NONE for lmem in small-BAR modeJordan Justen1-2/+8
2022-07-21iris/bufmgr: Add all_vram_mappable which is currently always trueJordan Justen1-0/+2
2022-07-21iris/resource: Avoid mapping when not needed in iris_resource_init_aux_buf()Jordan Justen1-11/+30
2022-07-21iris/resource: Assert that DG2 CCS buffers don't also try to set BO_ALLOC_SMEMJordan Justen1-1/+3
2022-07-21intel/dev: Add intel_vram_all_mappable()Jordan Justen1-0/+6
2022-07-21intel/tools: Print unmappable region info in intel_dev_infoJordan Justen1-2/+16
2022-07-21intel/dev: Add vram.unmappable.size region infoJordan Justen2-2/+3
2022-07-21intel/dev: deal with i915 unallocated_size on smemLionel Landwerlin1-3/+8
2022-07-21ttn: set dest_type for TXQMarek Olšák1-0/+2
2022-07-21ir3: Stop using nir_legalize_16bit_sampler_srcs.Georg Lehmann1-23/+2
2022-07-21nir/lower_mediump: Add an option to only fold if all tex sources can be folded.Georg Lehmann2-5/+11
2022-07-21nir: Rewrite and merge 16bit tex folding pass with 16bit image folding pass.Georg Lehmann6-247/+253
2022-07-21ir3: Lower alu to scalar if nir_legalize_16bit_sampler_srcs made progress.Georg Lehmann1-1/+5
2022-07-21ir3: Only run 16bit tex NIR passes on a5xx+.Georg Lehmann1-1/+1
2022-07-21zink: add env var to abort on device-lost if no reset callback is setMike Blumenkrantz4-0/+18
2022-07-21gallium/tests: Remove format desc null checksKonstantin Seurer1-12/+10
2022-07-21util/format: Remove format desc null checksKonstantin Seurer2-13/+0
2022-07-21pvr: Remove format desc null checkKonstantin Seurer1-9/+1
2022-07-21virgl: Remove format desc null checksKonstantin Seurer1-4/+0
2022-07-21softpipe: Remove format desc null checkKonstantin Seurer1-2/+0
2022-07-21radeonsi: Remove format desc null checksKonstantin Seurer1-7/+0
2022-07-21r600: Remove format desc null checksKonstantin Seurer3-12/+0
2022-07-21r300: Remove format desc null checkKonstantin Seurer1-2/+0
2022-07-21panfrost: Remove format desc null checkKonstantin Seurer1-3/+0
2022-07-21llvmpipe: Remove format desc null checksKonstantin Seurer3-6/+0
2022-07-21etnaviv: Remove format desc null checkKonstantin Seurer1-2/+0
2022-07-21agx: Remove format desc null checkKonstantin Seurer1-7/+0
2022-07-21util: Remove format desc null checkKonstantin Seurer1-8/+5
2022-07-21tgsi: Remove format desc null checkKonstantin Seurer2-3/+1
2022-07-21gallivm: Remove format desc null checksKonstantin Seurer1-9/+6
2022-07-21turnip: Remove format desc null assertKonstantin Seurer1-2/+2
2022-07-21v3dv: Remove format desc null assertsKonstantin Seurer1-2/+0
2022-07-21radv: Use desc->formatKonstantin Seurer1-2/+1
2022-07-21radv: Remove format desc null checksKonstantin Seurer2-9/+6
2022-07-21util/format: Assert that formats are validKonstantin Seurer1-8/+4
2022-07-21util/format: Use an explicit length for the descsKonstantin Seurer1-4/+4
2022-07-21radv: only force 1x sample for Bresenham lines when pipeline draws linesSamuel Pitoiset2-19/+28
2022-07-21ci/lava: Increase boot timeoutGuilherme Gallo1-2/+7
2022-07-21ci/turnip: Add a bit of spilling-vs-ballot testing on a618.Emma Anholt2-1/+4
2022-07-21freedreno: Enable A619Konrad Dybcio1-1/+2
2022-07-20util: Gate simple_mtx_assert_locked on !NDEBUGAlyssa Rosenzweig1-1/+1