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AgeCommit message (Expand)AuthorFilesLines
2021-12-13intel/compiler: Assert that unsupported tg4 offsets were lowered for XeHPlower-tg4-offsetRafael Antognolli1-0/+5
2021-12-13intel/compiler: Use nir_lower_tex_options::lower_offset_filter for tg4 on XeHPJordan Justen1-0/+30
2021-12-13nir/lower_tex: Add filter for tex offset loweringJordan Justen2-1/+14
2021-12-13iris: Align buffer VMA to 2MiB for XeHPJordan Justen1-1/+3
2021-12-13anv: Align buffer VMA to 2MiB for XeHPJordan Justen1-0/+6
2021-12-13iris: Not all gfx12+ have aux_map_ctxJordan Justen1-4/+5
2021-12-13glapi: Never use dllimport/dllexport for TLS vars on WindowsJesse Natalie1-1/+2
2021-12-13radv,aco: don't lower some ffma instructionsRhys Perry1-3/+3
2021-12-13radv,aco: implement nir_op_ffmaRhys Perry4-3/+32
2021-12-13aco: swap multiplication operands if needed to create v_fmac_f32/etcRhys Perry1-4/+11
2021-12-13aco: swap operands if necessary to create v_madak/v_fmaakRhys Perry1-22/+38
2021-12-13aco: create v_fmamk_f32/v_fmaak_f32 from nir_op_ffmaRhys Perry1-0/+7
2021-12-13aco: use more predictable tiebreaker when forming MADsRhys Perry1-1/+8
2021-12-13radv: ignore dynamic inheritance if the render pass isn't NULLSamuel Pitoiset1-11/+12
2021-12-13radv: fix dynamic rendering inheritance if the subpass index isn't 0Samuel Pitoiset1-10/+15
2021-12-13radv: enable lower_lod_zero_widthSamuel Pitoiset1-0/+1
2021-12-13nir/lower_tex: add lower_lod_zero_widthSamuel Pitoiset2-0/+44
2021-12-13radeonsi: use max_zplanes after the last writePierre-Eric Pelloux-Prayer1-2/+2
2021-12-13radeonsi: silence a warningPierre-Eric Pelloux-Prayer1-1/+1
2021-12-13radeonsi: fix fast clear / depth decompression corruptionPierre-Eric Pelloux-Prayer3-2/+26
2021-12-13nir: limit lower_clip_cull_distance_arrays input to traditional stagesMarcin Ślusarz1-1/+2
2021-12-13v3dv: Fix V3DV_HAS_SURFACE preprocessor conditionRoman Stratiienko1-6/+8
2021-12-13intel/compiler: Use a struct for brw_compile_bs parametersCaio Oliveira3-30/+58
2021-12-13intel/compiler: Use a struct for brw_compile_gs parametersCaio Oliveira5-43/+68
2021-12-13intel/compiler: Use a struct for brw_compile_tes parametersCaio Oliveira5-43/+69
2021-12-13intel/compiler: Use a struct for brw_compile_tcs parametersCaio Oliveira5-38/+62
2021-12-13crocus: cleanup bo exports for external objectsDave Airlie1-0/+10
2021-12-11radeonsi: unroll loops of up to 128 iterationsMarek Olšák3-9/+5
2021-12-11radeonsi: add shader profiles that disable binningMarek Olšák5-1/+34
2021-12-11radeonsi: print more stats for shader-dbMarek Olšák1-2/+4
2021-12-11radeonsi: add Wave32 heuristics and shader profilesMarek Olšák5-5/+123
2021-12-11glsl: fix setting compiled_source_sha1 without a shader cacheMarek Olšák1-1/+2
2021-12-11nir: add nir_has_divergent_loop functionMarek Olšák2-0/+17
2021-12-11nir: serialize divergent fieldsMarek Olšák1-1/+7
2021-12-11nir: disable a NIR test due to undebuggable & locally unreproducible CI failuresMarek Olšák1-1/+1
2021-12-11nir: handle more intrinsics in divergence analysisMarek Olšák1-0/+5
2021-12-11drisw: do an MSAA resolve when copying the backbufferItalo Nicola1-0/+7
2021-12-11virgl: flush cmd buffer when flushing frontbufferItalo Nicola3-4/+7
2021-12-11virgl/vtest: implement resource_create_frontItalo Nicola6-13/+45
2021-12-11virgl/vtest: use correct resource stride in flush_frontbufferItalo Nicola1-1/+2
2021-12-11util: Use ralloc for strings in cache testCaio Oliveira1-22/+29
2021-12-11util: Convert cache test to use gtestCaio Oliveira3-192/+80
2021-12-11intel/dev: Add gtt_size to devinfoJason Ekstrand7-63/+29
2021-12-11anv: Stop doing too much per-sample shadingJason Ekstrand1-21/+19
2021-12-11iris: Update the initial CCS state on XeHPNanley Chery1-10/+26
2021-12-11iris: Modify the comment about zeroing CCSNanley Chery1-8/+5
2021-12-11iris: Don't assert a NULL aux BO during aux configNanley Chery1-2/+0
2021-12-11iris: Don't allocate and initialize CCS on XeHPNanley Chery1-7/+15
2021-12-11iris: Drop row pitch param from iris_get_ccs_surfNanley Chery1-5/+3
2021-12-11iris: Don't allocate a clear color BO for some Z/SNanley Chery1-8/+22