diff options
author | Rohan Garg <rohan.garg@intel.com> | 2023-09-25 16:09:42 +0200 |
---|---|---|
committer | Jordan Justen <jordan.l.justen@intel.com> | 2024-08-01 00:33:19 -0700 |
commit | c4d73f8fe6c2ee8ddff3ed9f06cf0126fe36cda8 (patch) | |
tree | b01cfbf8aaf3369477ac9d750975abcbbc7b8e4e | |
parent | 2824f5779c702ec30e4e0a6c02020f765db1c364 (diff) |
intel/compiler: Ensure that we don't emit valid EU code for WA 14017715663
The compiler lowes away most of the byte instructions. So we don't need
to do much for this WA apart from adding a test in the EU validation
code.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
-rw-r--r-- | src/intel/compiler/test_eu_validate.cpp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index 8940280b06f..0cc4b6e125d 100644 --- a/src/intel/compiler/test_eu_validate.cpp +++ b/src/intel/compiler/test_eu_validate.cpp @@ -3459,3 +3459,32 @@ TEST_P(validation_test, dpas_src_subreg_nr) clear_instructions(p); } } + +TEST_P(validation_test, wa_14017715663) +{ + if (devinfo.ver < 20) + return; + + /* Implement checks for Wa 14017715663 + * + * Compiler must not produce instruction with the following condition: + * + * Dst is byte datatype with a stride greater or equal to 4 and Src1 operand is + * word datatype with odd offset. Instead a move instruction must be used with + * such pattern to align to a even offset. + */ + + brw_ADD(p, g0, g0, g0); + brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16); + brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_B); + brw_inst_set_dst_da_reg_nr(&devinfo, last_inst, 16); + brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 2); + brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_B); + brw_inst_set_src0_da_reg_nr(&devinfo, last_inst, 1); + brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 1); + brw_inst_set_src1_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_TYPE_W); + brw_inst_set_src1_da_reg_nr(&devinfo, last_inst, 3); + brw_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 9); + + EXPECT_FALSE(validate(p)); +} |