diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2020-01-09 15:50:14 -0800 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2020-01-13 23:19:56 -0800 |
| commit | e6151c460cd6ed3f5142272eedeac66c3ca507b0 (patch) | |
| tree | 34de8d09a19b62b0c8a24178d54b9ff4f89a3b31 | |
| parent | a2b444eec448a13321963200e1825b9820c043f5 (diff) | |
iris, anv: Change default for Small PL for gen12 WAwa-1406941453
Ref: GEN:BUG:1406941453
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 18 | ||||
| -rw-r--r-- | src/intel/genxml/gen12.xml | 7 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 13 |
3 files changed, 38 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 582611d3a04..2ea077300da 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -967,6 +967,15 @@ iris_init_render_context(struct iris_batch *batch) iris_upload_slice_hashing_state(batch); #endif +#if GEN_GEN == 12 + iris_pack_state(GENX(SAMPLER_MODE), ®_val, reg) { + /* GEN:BUG:1406941453 */ + reg.SmallPL = true; + reg.SmallPLMask = true; + } + iris_emit_lri(batch, SAMPLER_MODE, reg_val); +#endif + /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid * changing it dynamically. We set it to the maximum size here, and * instead include the render target dimensions in the viewport, so @@ -1020,6 +1029,15 @@ iris_init_compute_context(struct iris_batch *batch) init_state_base_address(batch); +#if GEN_GEN == 12 + iris_pack_state(GENX(SAMPLER_MODE), ®_val, reg) { + /* GEN:BUG:1406941453 */ + reg.SmallPL = true; + reg.SmallPLMask = true; + } + iris_emit_lri(batch, SAMPLER_MODE, reg_val); +#endif + #if GEN_GEN == 9 if (devinfo->is_geminilake) init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU); diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index e17fa1a1863..6ed406c950d 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -7217,6 +7217,13 @@ <field name="State Cache Redirect To CS Section Enable Mask" start="27" end="27" type="bool"/> </register> + <register name="SAMPLER_MODE" length="1" num="0xe18c"> + <field name="Headerless Message for Pre-emptable Contexts" start="5" end="5" type="bool"/> + <field name="Headerless Message for Pre-emptable Contexts Mask" start="21" end="21" type="bool"/> + <field name="Small PL" start="15" end="15" type="bool"/> + <field name="Small PL Mask" start="31" end="31" type="bool"/> + </register> + <register name="SO_NUM_PRIMS_WRITTEN0" length="2" num="0x5200"> <field name="Num Prims Written Count" start="0" end="63" type="uint"/> </register> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 78e018762cb..fdd2142a6ee 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -233,6 +233,19 @@ genX(init_device_state)(struct anv_device *device) anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp); #endif +#if GEN_GEN == 12 + uint32_t sampler_mode; + anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE), + /* GEN:BUG:1406941453 */ + .SmallPL = true, + .SmallPLMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(SAMPLER_MODE_num); + lri.DataDWord = sampler_mode; + } +#endif + #if GEN_GEN == 10 gen10_emit_wa_lri_to_cache_mode_zero(&batch); #endif |