diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2021-11-02 03:36:04 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2021-11-04 21:23:21 -0700 |
| commit | 77a07874e30f2f324557b85a5c86028529f7ccc3 (patch) | |
| tree | 0b046bc3bf5d82d409e09c2a7c13e97492c1ed43 | |
| parent | 833c0394e01b178a33ce9f468e50408ff4970428 (diff) | |
iris: Use mi_builder in iris_load_indirect_location()iris-compute-indirect-mi_builder
For example, this allows us to take advantage of command-streamer
based register offsets in mi_builder.
Ref: 06cf838cbdc ("intel/mi_builder: Support gen11 command-streamer based register offsets")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 581580682ad..342bb21d94e 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6929,18 +6929,14 @@ iris_load_indirect_location(struct iris_context *ice, struct iris_state_ref *grid_size = &ice->state.grid_size; struct iris_bo *bo = iris_resource_bo(grid_size->res); - iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { - lrm.RegisterAddress = GPGPU_DISPATCHDIMX; - lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 0); - } - iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { - lrm.RegisterAddress = GPGPU_DISPATCHDIMY; - lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 4); - } - iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { - lrm.RegisterAddress = GPGPU_DISPATCHDIMZ; - lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 8); - } + struct mi_builder b; + mi_builder_init(&b, &batch->screen->devinfo, batch); + struct mi_value size_x = mi_mem32(ro_bo(bo, grid_size->offset + 0)); + struct mi_value size_y = mi_mem32(ro_bo(bo, grid_size->offset + 4)); + struct mi_value size_z = mi_mem32(ro_bo(bo, grid_size->offset + 8)); + mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMX), size_x); + mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMY), size_y); + mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMZ), size_z); } #if GFX_VERx10 >= 125 |