diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2022-04-30 02:30:57 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2022-07-26 16:15:49 -0700 |
| commit | dcf7957ae4e919fd8430700b7765b418c4732fa5 (patch) | |
| tree | 1fa7826471672438866e14040ee21770de68602c | |
| parent | 4cfa777e393705b40cebd0a4cd76aa827ce8b194 (diff) | |
intel/dev: Enable remaining DG2 and ATS-M device IDsdg2-pci-ids
Mostly Matt Roper's kernel patch commit message:
The device IDs here are associated with DG2 add-in cards. We need to
wait for some additional functionality (e.g., small BAR recovery) to
land before we're ready to upstream these.
Ref: https://patchwork.freedesktop.org/patch/483381/?series=103098&rev=1
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | include/pci_ids/iris_pci_ids.h | 37 |
1 files changed, 18 insertions, 19 deletions
diff --git a/include/pci_ids/iris_pci_ids.h b/include/pci_ids/iris_pci_ids.h index 9f460deb350..cfd649ce81a 100644 --- a/include/pci_ids/iris_pci_ids.h +++ b/include/pci_ids/iris_pci_ids.h @@ -221,14 +221,13 @@ CHIPSET(0x4907, sg1, "SG1", "Intel(R) Graphics") CHIPSET(0x4908, dg1, "DG1", "Intel(R) Graphics") CHIPSET(0x4909, dg1, "DG1", "Intel(R) Graphics") -/* Commented devices are waiting on i915 upstream support */ -/* CHIPSET(0x4f80, dg2_g10, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x4f81, dg2_g10, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x4f82, dg2_g10, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x4f83, dg2_g10, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x4f84, dg2_g10, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x4f87, dg2_g11, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x4f88, dg2_g11, "DG2", "Intel(R) Graphics") */ +CHIPSET(0x4f80, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x4f81, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x4f82, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x4f83, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x4f84, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x4f87, dg2_g11, "DG2", "Intel(R) Graphics") +CHIPSET(0x4f88, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x5690, dg2_g10, "DG2", "Intel(R) Graphics") CHIPSET(0x5691, dg2_g10, "DG2", "Intel(R) Graphics") CHIPSET(0x5692, dg2_g10, "DG2", "Intel(R) Graphics") @@ -237,16 +236,16 @@ CHIPSET(0x5694, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x5695, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x5696, dg2_g12, "DG2", "Intel(R) Graphics") CHIPSET(0x5697, dg2_g12, "DG2", "Intel(R) Graphics") -/* CHIPSET(0x56a0, dg2_g10, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x56a1, dg2_g10, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x56a2, dg2_g10, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x56a3, dg2_g12, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x56a4, dg2_g12, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x56a5, dg2_g11, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x56a6, dg2_g11, "DG2", "Intel(R) Graphics") */ +CHIPSET(0x56a0, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x56a1, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x56a2, dg2_g10, "DG2", "Intel(R) Graphics") +CHIPSET(0x56a3, dg2_g12, "DG2", "Intel(R) Graphics") +CHIPSET(0x56a4, dg2_g12, "DG2", "Intel(R) Graphics") +CHIPSET(0x56a5, dg2_g11, "DG2", "Intel(R) Graphics") +CHIPSET(0x56a6, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x56b0, dg2_g11, "DG2", "Intel(R) Graphics") -/* CHIPSET(0x56b1, dg2_g11, "DG2", "Intel(R) Graphics") */ +CHIPSET(0x56b1, dg2_g11, "DG2", "Intel(R) Graphics") CHIPSET(0x56b2, dg2_g12, "DG2", "Intel(R) Graphics") -/* CHIPSET(0x56b3, dg2_g12, "DG2", "Intel(R) Graphics") */ -/* CHIPSET(0x56c0, dg2_g10, "ATS-M", "Intel(R) Graphics") */ -/* CHIPSET(0x56c1, dg2_g11, "ATS-M", "Intel(R) Graphics") */ +CHIPSET(0x56b3, dg2_g12, "DG2", "Intel(R) Graphics") +CHIPSET(0x56c0, dg2_g10, "ATS-M", "Intel(R) Graphics") +CHIPSET(0x56c1, dg2_g11, "ATS-M", "Intel(R) Graphics") |