diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2022-01-06 13:33:07 -0800 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2022-01-10 11:00:44 -0800 |
| commit | 1659b8c5d39e3e6f76a9185a4773a9cba595ea73 (patch) | |
| tree | 98ae4701df09461165a3570d0991c009eee3a9de | |
| parent | d799a4be27a30c8d7171a7b896ba229432c08698 (diff) | |
isl: Don't enable HDC:L1 caches on DG2dg2-hdc-l1
The MOCS entry used for this on Tigerlake doesn't exist on DG2.
Ref: aca31baafc0 ("isl: Enable Tigerlake HDC:L1 caches via MOCS in various cases.")
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | src/intel/isl/isl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index cc775ea5c3f..0c70ce680e6 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -170,7 +170,7 @@ isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage, if (external) return dev->mocs.external; - if (dev->info->ver >= 12 && dev->info->platform != INTEL_PLATFORM_DG1) { + if (dev->info->verx10 == 120 && dev->info->platform != INTEL_PLATFORM_DG1) { if (usage & ISL_SURF_USAGE_STAGING_BIT) return dev->mocs.internal; |