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-rw-r--r--src/mesa/drivers/dri/i965/brw_curbe.c3
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw.c7
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c9
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c33
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.cpp20
-rw-r--r--src/mesa/drivers/dri/i965/gen6_depth_state.c13
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp32
-rw-r--r--src/mesa/drivers/dri/i965/gen7_disable.c16
-rw-r--r--src/mesa/drivers/dri/i965/gen7_misc_state.c13
-rw-r--r--src/mesa/drivers/dri/i965/gen8_depth_state.c21
-rw-r--r--src/mesa/drivers/dri/i965/gen8_disable.c20
-rw-r--r--src/mesa/drivers/dri/i965/gen8_draw_upload.c15
-rw-r--r--src/mesa/drivers/dri/i965/gen8_sf_state.c6
-rw-r--r--src/mesa/drivers/dri/i965/intel_batchbuffer.h8
-rw-r--r--src/mesa/drivers/dri/i965/intel_blit.c14
-rw-r--r--src/mesa/drivers/dri/i965/intel_extensions.c14
16 files changed, 146 insertions, 98 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index c3d3b9d213..459a35eee4 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -200,6 +200,7 @@ brw_upload_constant_buffer(struct brw_context *brw)
gl_constant_value *buf;
GLuint i;
gl_clip_plane *clip_planes;
+ BATCH_PTR_DECL;
if (sz == 0) {
goto emit;
@@ -293,7 +294,7 @@ emit:
* [re]issue a CONSTANT_BUFFER command before CURBE data can be used
* in the pipeline."
*/
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
if (brw->curbe.total_size == 0) {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2));
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index c581cc0f5c..0acf5a25d4 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -178,6 +178,7 @@ static void brw_emit_prim(struct brw_context *brw,
int verts_per_instance;
int vertex_access_type;
int indirect_flag;
+ BATCH_PTR_DECL;
DBG("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode),
prim->start, prim->count);
@@ -241,7 +242,7 @@ static void brw_emit_prim(struct brw_context *brw,
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 12);
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
OUT_BATCH(0);
@@ -254,11 +255,11 @@ static void brw_emit_prim(struct brw_context *brw,
if (brw->gen >= 7) {
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2) | indirect_flag);
OUT_BATCH(hw_prim | vertex_access_type);
} else {
- BEGIN_BATCH(6);
+ BEGIN_BATCH_N(6);
OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
hw_prim << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
vertex_access_type);
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 6e0cf3e353..bf767772f0 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -632,7 +632,8 @@ emit_vertex_buffer_state(struct brw_context *brw,
unsigned bo_ending_address,
unsigned bo_offset,
unsigned stride,
- unsigned step_rate)
+ unsigned step_rate,
+ BATCH_PTR_DECL)
{
struct gl_context *ctx = &brw->ctx;
uint32_t dw0;
@@ -727,7 +728,8 @@ static void brw_emit_vertices(struct brw_context *brw)
struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
emit_vertex_buffer_state(brw, i, buffer->bo, buffer->bo->size - 1,
buffer->offset, buffer->stride,
- buffer->step_rate);
+ buffer->step_rate,
+ BATCH_PTR);
}
@@ -737,7 +739,8 @@ static void brw_emit_vertices(struct brw_context *brw)
brw->draw.draw_params_bo->size - 1,
brw->draw.draw_params_offset,
0, /* stride */
- 0); /* step rate */
+ 0, /* step rate */
+ BATCH_PTR);
}
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index a405eb25f6..9f8c5500d6 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -575,7 +575,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
* disabled) as Hierarchical Depth Buffer Enable
*/
bool enable_hiz_ss = hiz || separate_stencil;
-
+ BATCH_PTR_DECL;
/* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
* non-pipelined state that will need the PIPE_CONTROL workaround.
@@ -593,7 +593,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
else
len = 5;
- BEGIN_BATCH(len);
+ BEGIN_BATCH_N(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
(depthbuffer_format << 18) |
@@ -638,7 +638,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
/* Emit hiz buffer. */
if (hiz) {
struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(hiz_mt->pitch - 1);
OUT_RELOC(hiz_mt->bo,
@@ -646,7 +646,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
brw->depthstencil.hiz_offset);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -655,7 +655,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
/* Emit stencil buffer. */
if (separate_stencil) {
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
/* The stencil buffer has quirky pitch requirements. From Vol 2a,
* 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
@@ -668,7 +668,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
brw->depthstencil.stencil_offset);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -688,7 +688,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
GEN5_DEPTH_CLEAR_VALID |
(2 - 2));
@@ -882,6 +882,7 @@ void
brw_upload_invariant_state(struct brw_context *brw)
{
const bool is_965 = brw->gen == 4 && !brw->is_g4x;
+ BATCH_PTR_DECL;
/* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
if (brw->gen == 6)
@@ -890,26 +891,26 @@ brw_upload_invariant_state(struct brw_context *brw)
/* Select the 3D pipeline (as opposed to media) */
const uint32_t _3DSTATE_PIPELINE_SELECT =
is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
- BEGIN_BATCH(1);
+ BEGIN_BATCH_N(1);
OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | (brw->gen >= 9 ? (3 << 8) : 0));
ADVANCE_BATCH();
if (brw->gen < 6) {
/* Disable depth offset clamping. */
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
OUT_BATCH_F(0.0);
ADVANCE_BATCH();
}
if (brw->gen >= 8) {
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
@@ -917,7 +918,7 @@ brw_upload_invariant_state(struct brw_context *brw)
const uint32_t _3DSTATE_VF_STATISTICS =
is_965 ? GEN4_3DSTATE_VF_STATISTICS : GM45_3DSTATE_VF_STATISTICS;
- BEGIN_BATCH(1);
+ BEGIN_BATCH_N(1);
OUT_BATCH(_3DSTATE_VF_STATISTICS << 16 | 1);
ADVANCE_BATCH();
}
@@ -942,6 +943,8 @@ const struct brw_tracked_state brw_invariant_state = {
*/
static void upload_state_base_address( struct brw_context *brw )
{
+ BATCH_PTR_DECL;
+
/* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
* vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
* programmed prior to STATE_BASE_ADDRESS.
@@ -957,7 +960,7 @@ static void upload_state_base_address( struct brw_context *brw )
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
- BEGIN_BATCH(10);
+ BEGIN_BATCH_N(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
OUT_BATCH(mocs << 8 | /* General State Memory Object Control State */
mocs << 4 | /* Stateless Data Port Access Memory Object Control State */
@@ -995,7 +998,7 @@ static void upload_state_base_address( struct brw_context *brw )
OUT_BATCH(1); /* Instruction access upper bound */
ADVANCE_BATCH();
} else if (brw->gen == 5) {
- BEGIN_BATCH(8);
+ BEGIN_BATCH_N(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
@@ -1008,7 +1011,7 @@ static void upload_state_base_address( struct brw_context *brw )
OUT_BATCH(1); /* Instruction access upper bound */
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(6);
+ BEGIN_BATCH_N(6);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_BATCH(1); /* General state base address */
OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index d4aa955e2d..d1af2452c0 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -517,6 +517,8 @@ void
gen6_blorp_emit_vs_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
+ BATCH_PTR_DECL;
+
if (brw->gen == 6) {
/* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
@@ -530,7 +532,7 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw,
}
/* Disable the push constant buffers. */
- BEGIN_BATCH(5);
+ BEGIN_BATCH_N(5);
OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -538,7 +540,7 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(6);
+ BEGIN_BATCH_N(6);
OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -557,8 +559,10 @@ void
gen6_blorp_emit_gs_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
+ BATCH_PTR_DECL;
+
/* Disable all the constant buffers. */
- BEGIN_BATCH(5);
+ BEGIN_BATCH_N(5);
OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -566,7 +570,7 @@ gen6_blorp_emit_gs_disable(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -782,6 +786,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
GLenum gl_target = params->depth.mt->target;
unsigned int lod;
+ //BATCH_PTR_DECL;
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -895,8 +900,9 @@ gen6_blorp_emit_depth_disable(struct brw_context *brw,
{
intel_emit_post_sync_nonzero_flush(brw);
intel_emit_depth_stall_flushes(brw);
+ BATCH_PTR_DECL;
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
(BRW_SURFACE_NULL << 29));
@@ -907,13 +913,13 @@ gen6_blorp_emit_depth_disable(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index f92c1afe64..37598cd6fc 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -53,6 +53,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
const struct intel_renderbuffer *irb = NULL;
const struct gl_renderbuffer *rb = NULL;
+ BATCH_PTR_DECL;
/* Enable the hiz bit if we're doing separate stencil, because it and the
* separate stencil bit must have the same value. From Section 2.11.5.6.1.1
@@ -108,7 +109,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
height = mt->logical_height0;
}
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
/* 3DSTATE_DEPTH_BUFFER dw0 */
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
@@ -172,7 +173,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
false);
}
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(hiz_mt->pitch - 1);
OUT_RELOC(hiz_mt->bo,
@@ -180,7 +181,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
offset);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -209,7 +210,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
}
}
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
/* The stencil buffer has quirky pitch requirements. From Vol 2a,
* 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
@@ -222,7 +223,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
offset);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -240,7 +241,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
*/
intel_emit_post_sync_nonzero_flush(brw);
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
GEN5_DEPTH_CLEAR_VALID |
(2 - 2));
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 206a6ff6d5..98ebd52211 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -231,7 +231,9 @@ static void
gen7_blorp_emit_vs_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
- BEGIN_BATCH(7);
+ BATCH_PTR_DECL;
+
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -241,7 +243,7 @@ gen7_blorp_emit_vs_disable(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(6);
+ BEGIN_BATCH_N(6);
OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -260,7 +262,9 @@ static void
gen7_blorp_emit_hs_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
- BEGIN_BATCH(7);
+ BATCH_PTR_DECL;
+
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -270,7 +274,7 @@ gen7_blorp_emit_hs_disable(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -307,7 +311,9 @@ static void
gen7_blorp_emit_ds_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
- BEGIN_BATCH(7);
+ BATCH_PTR_DECL;
+
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -317,7 +323,7 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(6);
+ BEGIN_BATCH_N(6);
OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -335,7 +341,9 @@ static void
gen7_blorp_emit_gs_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
- BEGIN_BATCH(7);
+ BATCH_PTR_DECL;
+
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -360,7 +368,7 @@ gen7_blorp_emit_gs_disable(struct brw_context *brw,
if (!brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
gen7_emit_cs_stall_flush(brw);
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -722,9 +730,11 @@ static void
gen7_blorp_emit_depth_disable(struct brw_context *brw,
const brw_blorp_params *params)
{
+ BATCH_PTR_DECL;
+
intel_emit_depth_stall_flushes(brw);
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
OUT_BATCH(0);
@@ -734,13 +744,13 @@ gen7_blorp_emit_depth_disable(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_disable.c b/src/mesa/drivers/dri/i965/gen7_disable.c
index 2c43cd77f0..fe17589d0f 100644
--- a/src/mesa/drivers/dri/i965/gen7_disable.c
+++ b/src/mesa/drivers/dri/i965/gen7_disable.c
@@ -29,8 +29,10 @@
static void
disable_stages(struct brw_context *brw)
{
+ BATCH_PTR_DECL;
+
/* Disable the HS Unit */
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -40,7 +42,7 @@ disable_stages(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -50,13 +52,13 @@ disable_stages(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_HS << 16 | (2 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
/* Disable the TE */
- BEGIN_BATCH(4);
+ BEGIN_BATCH_N(4);
OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -64,7 +66,7 @@ disable_stages(struct brw_context *brw)
ADVANCE_BATCH();
/* Disable the DS Unit */
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -74,7 +76,7 @@ disable_stages(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(6);
+ BEGIN_BATCH_N(6);
OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -83,7 +85,7 @@ disable_stages(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_DS << 16 | (2 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 33d4ade4fe..c6d5e05c17 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -50,6 +50,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
const struct intel_renderbuffer *irb = NULL;
const struct gl_renderbuffer *rb = NULL;
+ BATCH_PTR_DECL;
/* Skip repeated NULL depth/stencil emits (think 2D rendering). */
if (!mt && brw->no_depth_or_stencil) {
@@ -100,7 +101,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
}
/* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
- BEGIN_BATCH(7);
+ BEGIN_BATCH_N(7);
/* 3DSTATE_DEPTH_BUFFER dw0 */
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
@@ -139,14 +140,14 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
ADVANCE_BATCH();
if (!hiz) {
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH((mocs << 25) |
(hiz_mt->pitch - 1));
@@ -158,7 +159,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
}
if (stencil_mt == NULL) {
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -166,7 +167,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
} else {
const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
/* The stencil buffer has quirky pitch requirements. From the
* Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
@@ -187,7 +188,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
ADVANCE_BATCH();
}
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
OUT_BATCH(1);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index e428089dd2..c62c33a9ea 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -50,6 +50,7 @@ emit_depth_packets(struct brw_context *brw,
uint32_t min_array_element)
{
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
+ BATCH_PTR_DECL;
/* Skip repeated NULL depth/stencil emits (think 2D rendering). */
if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
@@ -60,7 +61,7 @@ emit_depth_packets(struct brw_context *brw,
intel_emit_depth_stall_flushes(brw);
/* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
- BEGIN_BATCH(8);
+ BEGIN_BATCH_N(8);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
OUT_BATCH(depth_surface_type << 29 |
(depth_writable ? (1 << 28) : 0) |
@@ -82,7 +83,7 @@ emit_depth_packets(struct brw_context *brw,
ADVANCE_BATCH();
if (!hiz) {
- BEGIN_BATCH(5);
+ BEGIN_BATCH_N(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -90,7 +91,7 @@ emit_depth_packets(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(5);
+ BEGIN_BATCH_N(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH((depth_mt->hiz_mt->pitch - 1) | mocs_wb << 25);
OUT_RELOC64(depth_mt->hiz_mt->bo,
@@ -100,7 +101,7 @@ emit_depth_packets(struct brw_context *brw,
}
if (stencil_mt == NULL) {
- BEGIN_BATCH(5);
+ BEGIN_BATCH_N(5);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -108,7 +109,7 @@ emit_depth_packets(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(5);
+ BEGIN_BATCH_N(5);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
/* The stencil buffer has quirky pitch requirements. From the Graphics
* BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
@@ -133,7 +134,7 @@ emit_depth_packets(struct brw_context *brw,
ADVANCE_BATCH();
}
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
OUT_BATCH(1);
@@ -384,6 +385,8 @@ void
gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer, enum gen6_hiz_op op)
{
+ BATCH_PTR_DECL;
+
if (op == GEN6_HIZ_OP_NONE)
return;
@@ -428,7 +431,7 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
unsigned rect_width = ALIGN(minify(mt->logical_width0, level), 8);
unsigned rect_height = ALIGN(minify(mt->logical_height0, level), 4);
- BEGIN_BATCH(4);
+ BEGIN_BATCH_N(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(((rect_width - 1) & 0xffff) | ((rect_height - 1) << 16));
@@ -457,7 +460,7 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
if (mt->num_samples > 0)
dw1 |= SET_FIELD(ffs(mt->num_samples) - 1, GEN8_WM_HZ_NUM_SAMPLES);
- BEGIN_BATCH(5);
+ BEGIN_BATCH_N(5);
OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
OUT_BATCH(dw1);
OUT_BATCH(0);
@@ -475,7 +478,7 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
brw->batch.workaround_bo, 0, 0, 0);
/* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
- BEGIN_BATCH(5);
+ BEGIN_BATCH_N(5);
OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen8_disable.c b/src/mesa/drivers/dri/i965/gen8_disable.c
index da0d4a5fe7..a837de3211 100644
--- a/src/mesa/drivers/dri/i965/gen8_disable.c
+++ b/src/mesa/drivers/dri/i965/gen8_disable.c
@@ -29,7 +29,9 @@
static void
disable_stages(struct brw_context *brw)
{
- BEGIN_BATCH(5);
+ BATCH_PTR_DECL;
+
+ BEGIN_BATCH_N(5);
OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -38,7 +40,7 @@ disable_stages(struct brw_context *brw)
ADVANCE_BATCH();
/* Disable the HS Unit */
- BEGIN_BATCH(11);
+ BEGIN_BATCH_N(11);
OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (11 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -52,7 +54,7 @@ disable_stages(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(9);
+ BEGIN_BATCH_N(9);
OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -64,13 +66,13 @@ disable_stages(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_HS << 16 | (2 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
/* Disable the TE */
- BEGIN_BATCH(4);
+ BEGIN_BATCH_N(4);
OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -78,7 +80,7 @@ disable_stages(struct brw_context *brw)
ADVANCE_BATCH();
/* Disable the DS Unit */
- BEGIN_BATCH(11);
+ BEGIN_BATCH_N(11);
OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (11 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -93,18 +95,18 @@ disable_stages(struct brw_context *brw)
ADVANCE_BATCH();
int ds_pkt_len = brw->gen >= 9 ? 11 : 9;
- BEGIN_BATCH(ds_pkt_len);
+ BEGIN_BATCH_N(ds_pkt_len);
OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2));
for (int i = 0; i < ds_pkt_len - 1; i++)
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_DS << 16 | (2 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_WM_CHROMAKEY << 16 | (2 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index 0d6feec8ab..a869d157e3 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -40,6 +40,7 @@ gen8_emit_vertices(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
+ BATCH_PTR_DECL;
brw_prepare_vertices(brw);
brw_prepare_shader_draw_parameters(brw);
@@ -67,18 +68,18 @@ gen8_emit_vertices(struct brw_context *brw)
(vue << GEN8_SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT);
}
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2));
OUT_BATCH(dw1);
ADVANCE_BATCH();
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
OUT_BATCH(brw->vb.nr_buffers | GEN8_VF_INSTANCING_ENABLE);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
- BEGIN_BATCH(2);
+ BEGIN_BATCH_N(2);
OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2));
OUT_BATCH(0);
ADVANCE_BATCH();
@@ -92,7 +93,7 @@ gen8_emit_vertices(struct brw_context *brw)
* a VE loads from them.
*/
if (brw->vb.nr_enabled == 0) {
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (3 - 2));
OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
GEN6_VE0_VALID |
@@ -111,7 +112,7 @@ gen8_emit_vertices(struct brw_context *brw)
if (nr_buffers) {
assert(nr_buffers <= 33);
- BEGIN_BATCH(1 + 4 * nr_buffers);
+ BEGIN_BATCH_N(1 + 4 * nr_buffers);
OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4 * nr_buffers - 1));
for (unsigned i = 0; i < brw->vb.nr_buffers; i++) {
struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
@@ -147,7 +148,7 @@ gen8_emit_vertices(struct brw_context *brw)
struct brw_vertex_element *gen6_edgeflag_input = NULL;
- BEGIN_BATCH(1 + nr_elements * 2);
+ BEGIN_BATCH_N(1 + nr_elements * 2);
OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
for (unsigned i = 0; i < brw->vb.nr_enabled; i++) {
struct brw_vertex_element *input = brw->vb.enabled[i];
@@ -222,7 +223,7 @@ gen8_emit_vertices(struct brw_context *brw)
const struct brw_vertex_element *input = brw->vb.enabled[i];
const struct brw_vertex_buffer *buffer = &brw->vb.buffers[input->buffer];
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2));
OUT_BATCH(i | (buffer->step_rate ? GEN8_VF_INSTANCING_ENABLE : 0));
OUT_BATCH(buffer->step_rate);
diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 0e514c6101..8556d5c7e1 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -103,7 +103,9 @@ upload_sbe(struct brw_context *brw)
++input_index;
}
}
- BEGIN_BATCH(sbe_cmd_length);
+
+ BATCH_PTR_DECL;
+ BEGIN_BATCH_N(sbe_cmd_length);
OUT_BATCH(_3DSTATE_SBE << 16 | (sbe_cmd_length - 2));
OUT_BATCH(dw1);
OUT_BATCH(point_sprite_enables);
@@ -114,7 +116,7 @@ upload_sbe(struct brw_context *brw)
}
ADVANCE_BATCH();
- BEGIN_BATCH(11);
+ BEGIN_BATCH_N(11);
OUT_BATCH(_3DSTATE_SBE_SWIZ << 16 | (11 - 2));
/* Output DWords 1 through 8: */
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index a5efa0abdc..920bb775bf 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -202,8 +202,12 @@ intel_batchbuffer_begin_fast(struct brw_context *brw, int n, enum brw_gpu_ring r
}
-#define BEGIN_BATCH(n) uint32_t *__batch_p = intel_batchbuffer_begin_fast(brw, n, RENDER_RING)
-#define BEGIN_BATCH_BLT(n) uint32_t *__batch_p = intel_batchbuffer_begin_fast(brw, n, BLT_RING)
+#define BATCH_PTR __batch_p
+#define BATCH_PTR_DECL uint32_t *BATCH_PTR
+#define BEGIN_BATCH_N_R(n, t) __batch_p = (uint32_t *) intel_batchbuffer_begin_fast(brw, n, t)
+#define BEGIN_BATCH_N(n) BEGIN_BATCH_N_R(n, RENDER_RING)
+#define BEGIN_BATCH(n) uint32_t * BEGIN_BATCH_N(n)
+#define BEGIN_BATCH_BLT(n) uint32_t * BEGIN_BATCH_N_R(n, BLT_RING)
#define OUT_BATCH(d) *__batch_p++ = d
#define OUT_BATCH_F(f) *__batch_p++ = float_as_int(f)
#define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 4e810dd744..b59e2de2f9 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -101,7 +101,8 @@ br13_for_cpp(int cpp)
*/
static void
set_blitter_tiling(struct brw_context *brw,
- bool dst_y_tiled, bool src_y_tiled)
+ bool dst_y_tiled, bool src_y_tiled,
+ BATCH_PTR_DECL)
{
assert(brw->gen >= 6);
@@ -119,14 +120,14 @@ set_blitter_tiling(struct brw_context *brw,
}
#define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do { \
- BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
+ BEGIN_BATCH_N_R(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0), BLT_RING); \
if (dst_y_tiled || src_y_tiled) \
- set_blitter_tiling(brw, dst_y_tiled, src_y_tiled); \
+ set_blitter_tiling(brw, dst_y_tiled, src_y_tiled, BATCH_PTR); \
} while (0)
#define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do { \
if (dst_y_tiled || src_y_tiled) \
- set_blitter_tiling(brw, false, false); \
+ set_blitter_tiling(brw, false, false, BATCH_PTR); \
ADVANCE_BATCH(); \
} while (0)
@@ -355,6 +356,7 @@ intelEmitCopyBlit(struct brw_context *brw,
drm_intel_bo *aper_array[3];
bool dst_y_tiled = dst_tiling == I915_TILING_Y;
bool src_y_tiled = src_tiling == I915_TILING_Y;
+ BATCH_PTR_DECL;
if (dst_tiling != I915_TILING_NONE) {
if (dst_offset & 4095)
@@ -506,6 +508,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
{
int dwords = ALIGN(src_size, 8) / 4;
uint32_t opcode, br13, blit_cmd;
+ BATCH_PTR_DECL;
if (dst_tiling != I915_TILING_NONE) {
if (dst_offset & 4095)
@@ -543,7 +546,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
if (dst_tiling != I915_TILING_NONE)
blit_cmd |= XY_DST_TILED;
- BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
+ BEGIN_BATCH_N_R(xy_setup_blt_length + 3, BLT_RING);
OUT_BATCH(opcode | (xy_setup_blt_length - 2));
OUT_BATCH(br13);
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
@@ -641,6 +644,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
uint32_t BR13, CMD;
int pitch, cpp;
drm_intel_bo *aper_array[2];
+ BATCH_PTR_DECL;
pitch = mt->pitch;
cpp = mt->cpp;
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index bbbb76f3e4..87aef011fc 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -42,6 +42,8 @@
static bool
can_do_pipelined_register_writes(struct brw_context *brw)
{
+ BATCH_PTR_DECL;
+
/* Supposedly, Broadwell just works. */
if (brw->gen >= 8)
return true;
@@ -66,7 +68,7 @@ can_do_pipelined_register_writes(struct brw_context *brw)
drm_intel_bo_unmap(brw->batch.workaround_bo);
/* Write the register. */
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(reg);
OUT_BATCH(expected_value);
@@ -75,7 +77,7 @@ can_do_pipelined_register_writes(struct brw_context *brw)
intel_batchbuffer_emit_mi_flush(brw);
/* Save the register's value back to the buffer. */
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
OUT_RELOC(brw->batch.workaround_bo,
@@ -97,6 +99,8 @@ can_do_pipelined_register_writes(struct brw_context *brw)
static bool
can_write_oacontrol(struct brw_context *brw)
{
+ BATCH_PTR_DECL;
+
if (brw->gen < 6 || brw->gen >= 8)
return false;
@@ -116,7 +120,7 @@ can_write_oacontrol(struct brw_context *brw)
drm_intel_bo_unmap(brw->batch.workaround_bo);
/* Write OACONTROL. */
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(OACONTROL);
OUT_BATCH(expected_value);
@@ -125,7 +129,7 @@ can_write_oacontrol(struct brw_context *brw)
intel_batchbuffer_emit_mi_flush(brw);
/* Save the register's value back to the buffer. */
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(OACONTROL);
OUT_RELOC(brw->batch.workaround_bo,
@@ -136,7 +140,7 @@ can_write_oacontrol(struct brw_context *brw)
intel_batchbuffer_emit_mi_flush(brw);
/* Set OACONTROL back to zero (everything off). */
- BEGIN_BATCH(3);
+ BEGIN_BATCH_N(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(OACONTROL);
OUT_BATCH(0);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 00:52:23 +0000