diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2015-11-24 16:15:21 -0800 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2015-11-24 16:15:21 -0800 |
| commit | 74fece798edcd38194651e93274caed1b1b8a24c (patch) | |
| tree | f7021e0a17726e13b6f18ddc46da489fee967d89 | |
| parent | c58a919d57f6367fce746820554500c7f674089d (diff) | |
i965: Add PIPE_CONTROL_STALL_AT_SCOREBOARD to L3 pipe controlssimd32
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_l3_state.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 84ab11869b..050bb5f773 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -333,7 +333,8 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg) PIPE_CONTROL_INSTRUCTION_INVALIDATE | PIPE_CONTROL_DATA_CACHE_INVALIDATE | PIPE_CONTROL_NO_WRITE | - PIPE_CONTROL_CS_STALL); + PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_STALL_AT_SCOREBOARD); /* ...followed by a second stalling flush which guarantees that * invalidation is complete when the L3 configuration registers are @@ -342,7 +343,8 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg) brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DATA_CACHE_INVALIDATE | PIPE_CONTROL_NO_WRITE | - PIPE_CONTROL_CS_STALL); + PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_STALL_AT_SCOREBOARD); if (brw->gen >= 8) { assert(!cfg->n[L3P_IS] && !cfg->n[L3P_C] && !cfg->n[L3P_T]); |