diff options
Diffstat (limited to 'shared-core/radeon_drv.h')
| -rw-r--r-- | shared-core/radeon_drv.h | 79 |
1 files changed, 57 insertions, 22 deletions
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 502ba89b..635ad14b 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -31,8 +31,8 @@ #ifndef __RADEON_DRV_H__ #define __RADEON_DRV_H__ -#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */ -#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */ +#define GET_RING_HEAD(ring) DRM_READ32( (volatile u32 *) (ring)->head ) +#define SET_RING_HEAD(ring,val) DRM_WRITE32( (volatile u32 *) (ring)->head , (val)) typedef struct drm_radeon_freelist { unsigned int age; @@ -53,7 +53,6 @@ typedef struct drm_radeon_ring_buffer { int space; int high_mark; - drm_local_map_t *ring_rptr; } drm_radeon_ring_buffer_t; typedef struct drm_radeon_depth_clear_t { @@ -127,13 +126,13 @@ typedef struct drm_radeon_private { drm_radeon_depth_clear_t depth_clear; - drm_local_map_t *sarea; - drm_local_map_t *fb; - drm_local_map_t *mmio; - drm_local_map_t *cp_ring; - drm_local_map_t *ring_rptr; - drm_local_map_t *buffers; - drm_local_map_t *agp_textures; + drm_map_t *sarea; + drm_map_t *fb; + drm_map_t *mmio; + drm_map_t *cp_ring; + drm_map_t *ring_rptr; + drm_map_t *buffers; + drm_map_t *agp_textures; struct mem_block *agp_heap; struct mem_block *fb_heap; @@ -194,7 +193,6 @@ extern int radeon_emit_and_wait_irq(drm_device_t *dev); extern int radeon_wait_irq(drm_device_t *dev, int swi_nr); extern int radeon_emit_irq(drm_device_t *dev); -extern void radeon_do_release(drm_device_t *dev); /* Flags for stats.boxes */ @@ -268,10 +266,8 @@ extern void radeon_do_release(drm_device_t *dev); #define RADEON_SCRATCH_UMSK 0x0770 #define RADEON_SCRATCH_ADDR 0x0774 -#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) - #define GET_SCRATCH( x ) (dev_priv->writeback_works \ - ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ + ? DRM_READ32( &dev_priv->scratch[(x)] ) \ : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) @@ -690,10 +686,15 @@ extern void radeon_do_release(drm_device_t *dev); #define RADEON_RING_HIGH_MARK 128 -#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) -#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) -#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) + +#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) +#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg) + +#define RADEON_READ(reg) DRM_READ32( (volatile u32 *) RADEON_ADDR(reg) ) +#define RADEON_WRITE(reg,val) DRM_WRITE32( (volatile u32 *) RADEON_ADDR(reg), (val) ) + +#define RADEON_READ8(reg) DRM_READ8( (volatile u8 *) RADEON_ADDR(reg) ) +#define RADEON_WRITE8(reg,val) DRM_WRITE8( (volatile u8 *) RADEON_ADDR(reg), (val) ) #define RADEON_WRITE_PLL( addr, val ) \ do { \ @@ -826,10 +827,43 @@ do { \ #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; -#define BEGIN_RING( n ) do { \ +#if defined(__alpha__) +# define RADEON_PAD_RING 16 /* pad ring requests to 16 lw boundaries */ +#else +# define RADEON_PAD_RING 0 +#endif + +#if RADEON_PAD_RING +# define radeon_pad_size(n) \ + (((RADEON_PAD_RING) - ((n) % (RADEON_PAD_RING))) % (RADEON_PAD_RING)) +# define radeon_pad_ring() do { \ + if (RADEON_VERBOSE) { \ + DRM_INFO("Padding ring from %d (%x) with %d words\n", \ + write, write, radeon_pad_size(write)); \ + } \ + switch (radeon_pad_size(write)) { \ + case 0: /* aligned */ \ + break; \ + case 1: /* 1 word */ \ + OUT_RING(CP_PACKET2()); \ + break; \ + default: /* >= 2 words */ \ + OUT_RING(CP_PACKET3(0x1000, radeon_pad_size(write) - 1));\ + write = (write + radeon_pad_size(write)) & mask; \ + write &= mask; \ + break; \ + } \ +} while(0) +#else +# define radeon_pad_size(n) 0 +# define radeon_pad_ring() +#endif + +#define BEGIN_RING( req_n ) do { \ + int n = req_n + radeon_pad_size(req_n); \ if ( RADEON_VERBOSE ) { \ - DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ - n, __FUNCTION__ ); \ + DRM_INFO( "BEGIN_RING( %d (%d) ) in %s\n", \ + n, req_n, __FUNCTION__ ); \ } \ if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ COMMIT_RING(); \ @@ -846,6 +880,7 @@ do { \ DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ write, dev_priv->ring.tail ); \ } \ + radeon_pad_ring(); \ if (((dev_priv->ring.tail + _nr) & mask) != write) { \ DRM_ERROR( \ "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ @@ -857,7 +892,7 @@ do { \ #define COMMIT_RING() do { \ /* Flush writes to ring */ \ - DRM_READMEMORYBARRIER(dev_priv->mmio); \ + DRM_READMEMORYBARRIER(); \ GET_RING_HEAD( &dev_priv->ring ); \ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ /* read from PCI bus to ensure correct posting */ \ |