diff options
| author | Niels Ole Salscheider <niels_ole@salscheider-online.de> | 2013-12-18 19:11:44 +0100 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2013-12-22 01:41:02 +0100 |
| commit | 900ac63ee88a16b7fb7f0ca2b03a40259b8ebd84 (patch) | |
| tree | 630db35504cc8b7b2ac046ba84a0294803b82fc2 | |
| parent | 852db050b9ab0a2e525e7495ba6343051ad1bc1c (diff) | |
winsys/radeon: remove superfluous distinction of cases
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 20 |
1 files changed, 5 insertions, 15 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c index acb12b2498..d8ad297295 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c @@ -482,22 +482,12 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs, unsigned flags, ui /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements * r6xx, requires at least 4 dw alignment to avoid a hw bug. */ - if (flags & RADEON_FLUSH_COMPUTE) { - if (cs->ws->info.chip_class <= SI) { - while (rcs->cdw & 7) - OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */ - } else { - while (rcs->cdw & 7) - OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */ - } + if (cs->ws->info.chip_class <= SI) { + while (rcs->cdw & 7) + OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */ } else { - if (cs->ws->info.chip_class <= SI) { - while (rcs->cdw & 7) - OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */ - } else { - while (rcs->cdw & 7) - OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */ - } + while (rcs->cdw & 7) + OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */ } break; case RING_UVD: |