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authorAdam Jackson <ajax@nwnk.net>2006-05-18 23:48:57 +0000
committerAdam Jackson <ajax@nwnk.net>2006-05-18 23:48:57 +0000
commitc11cfcfaffc79be5686c666f881c4c08f69e1b86 (patch)
treea32e9e8f0de68752c92115ff1b0c9db6e1454f7d /hw
parentfa9a49a92db52de968d7147c71c6b9a8fd480f1e (diff)
Bug #6377: Ignore disabled BARs, and allow matching BARs aligned to less
than 16 bytes. (Felix Kühling, ATI)
Diffstat (limited to 'hw')
-rw-r--r--hw/xfree86/os-support/linux/lnx_pci.c26
1 files changed, 15 insertions, 11 deletions
diff --git a/hw/xfree86/os-support/linux/lnx_pci.c b/hw/xfree86/os-support/linux/lnx_pci.c
index cec9226c8..3505887bc 100644
--- a/hw/xfree86/os-support/linux/lnx_pci.c
+++ b/hw/xfree86/os-support/linux/lnx_pci.c
@@ -202,22 +202,26 @@ xf86GetOSOffsetFromPCI(PCITAG tag, int space, unsigned long base)
if (tag == pciTag(bus,dev,fn)) {
/* ok now look through all the BAR values of this device */
for (ndx=0; ndx<7; ndx++) {
- unsigned long savePtr;
- /*
- * remember to lop of the last 4bits of the BAR values as they are
- * memory attributes
- */
+ unsigned long savePtr, flagMask;
if (ndx == 6)
- savePtr = (0xFFFFFFF0) &
- pciReadLong(tag, PCI_CMD_BIOS_REG);
+ savePtr = pciReadLong(tag, PCI_CMD_BIOS_REG);
else /* this the ROM bar */
- savePtr = (0xFFFFFFF0) &
- pciReadLong(tag, PCI_CMD_BASE_REG + (0x4 * ndx));
+ savePtr = pciReadLong(tag, PCI_CMD_BASE_REG + (0x4 * ndx));
+ /* Ignore unset base addresses. The kernel may
+ * have reported non-zero size and address even
+ * if they are disabled (e.g. disabled ROM BAR).
+ */
+ if (savePtr == 0)
+ continue;
+ /* Remove memory attribute bits, different for IO
+ * and memory ranges. */
+ flagMask = (savePtr & 0x1) ? ~0x3UL : ~0xFUL;
+ savePtr &= flagMask;
/* find the index of the incoming base */
- if (base >= savePtr && base <= (savePtr + size[ndx])) {
+ if (base >= savePtr && base < (savePtr + size[ndx])) {
fclose(file);
- return (offset[ndx] & ~(0xFUL)) + (base - savePtr);
+ return (offset[ndx] & flagMask) + (base - savePtr);
}
}
}