diff options
| author | Nanley Chery <nanley.g.chery@intel.com> | 2019-05-22 14:10:23 -0700 |
|---|---|---|
| committer | Nanley Chery <nanley.g.chery@intel.com> | 2019-05-28 14:36:04 -0700 |
| commit | 6a869070af7df568ad5b23be66652a5b9955fee7 (patch) | |
| tree | 545b11601006061567571618808b00335eb66857 | |
| parent | 3868e1cf110a5d3b9b718cbfeea6b898c0015ea5 (diff) | |
fbo-generatemipmap-formats: Modify NPOT tex_width
The i965 driver's surface layout component (ISL) can calculate the
location of miplevels incorrectly when the surface is compressed. Set
the width to 257px to demonstrate this issue.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
| -rw-r--r-- | tests/fbo/fbo-generatemipmap-formats.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/tests/fbo/fbo-generatemipmap-formats.c b/tests/fbo/fbo-generatemipmap-formats.c index 9d41b6fe8..986a2d858 100644 --- a/tests/fbo/fbo-generatemipmap-formats.c +++ b/tests/fbo/fbo-generatemipmap-formats.c @@ -53,7 +53,10 @@ static void set_npot(bool new_npot) { npot = new_npot; if (npot) { - tex_width = 293; + /* Mipmapped compressed textures with a level 0 width of 257px + * demonstrated a surface layout bug in the i965 driver. + */ + tex_width = 257; tex_height = 277; } else { tex_width = 256; |