diff options
| author | Zhigang Gong <zhigang.gong@linux.intel.com> | 2013-08-12 15:53:43 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@linux.intel.com> | 2013-08-14 13:32:18 +0800 |
| commit | 98bfaa78f5968168d3b12a2a181e6d2aa026f500 (patch) | |
| tree | f9eb4bf5906232de423143b045be0495c59b575c /backend | |
| parent | 628baebaf0dd22a0fa949760f5553a1baa1fb43e (diff) | |
GBE: set temporary address register for read64 to U64.
Actually, we really use it as two DWORD rather than U64. But if
we don't set it to U64, in post scheduler, it doesn't know this
is a QWORD register and may cause incorrect scheduling.
We can easily trigger this bug when run compiler_vector_double16_load_store
with SIMD8 mode. This patch can fix the bug.
Signed-off-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Diffstat (limited to 'backend')
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 38f56b56..b0dada0c 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2088,7 +2088,7 @@ namespace gbe dst[dstID] = sel.selReg(sel.reg(FAMILY_DWORD)); for ( uint32_t valueID = 0; valueID < valueNum; ++dstID, ++valueID) dst[dstID] = sel.selReg(insn.getValue(valueID)); - sel.READ64(addr, sel.selReg(sel.reg(FAMILY_QWORD)), dst, valueNum + tmpRegNum, valueNum, bti); + sel.READ64(addr, sel.selReg(sel.reg(FAMILY_QWORD), ir::TYPE_U64), dst, valueNum + tmpRegNum, valueNum, bti); } void emitByteGather(Selection::Opaque &sel, |