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| author | Guo Yejun <yejun.guo@intel.com> | 2015-08-26 02:50:49 +0800 |
|---|---|---|
| committer | Yang Rong <rong.r.yang@intel.com> | 2015-08-27 14:37:34 +0800 |
| commit | 6d3306ab90a731ab79391505c7778b8ebae64dfe (patch) | |
| tree | 354d75acf559a23bef1acc7dd3eda5bca7dff111 /backend | |
| parent | 7f350383b61903f5f03d79354c49285a13cc832a (diff) | |
correct simd width when dst of simd_shuffle is scalar
originally, the dst of simd_shuffle is not uniform, but if it is
optimized as scalar, just use simd_width=1 to generate sel_op/asm
Signed-off-by: Guo Yejun <yejun.guo@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
Diffstat (limited to 'backend')
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index b84bb4bb..b0a7f570 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -5022,6 +5022,11 @@ namespace gbe } sel.push(); + if (sel.isScalarReg(insn.getDst(0))) { + sel.curr.execWidth = 1; + sel.curr.predicate = GEN_PREDICATE_NONE; + sel.curr.noMask = 1; + } if (src1.file == GEN_IMMEDIATE_VALUE) sel.SIMD_SHUFFLE(dst, src0, src1); else { |