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authorLuo Xionghu <xionghu.luo@intel.com>2014-09-15 08:23:37 +0800
committerZhigang Gong <zhigang.gong@intel.com>2014-09-26 12:56:37 +0800
commit13d8e51dca732758592f8f4826f0bc4d21ec5553 (patch)
tree19968b0d077020fc89009e1f2fcb6f61fda14d95 /backend/src/ir/instruction.cpp
parentc0ba37d62dcac92adfc309e73abd7e12a02d8498 (diff)
Add Gen IR WHILE.
Add Gen IR WHILE to mark the strucutred region. Signed-off-by: Luo Xionghu <xionghu.luo@intel.com> Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Diffstat (limited to 'backend/src/ir/instruction.cpp')
-rw-r--r--backend/src/ir/instruction.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp
index 2d86480e..e4e30ed6 100644
--- a/backend/src/ir/instruction.cpp
+++ b/backend/src/ir/instruction.cpp
@@ -349,7 +349,7 @@ namespace ir {
{
public:
INLINE BranchInstruction(Opcode op, LabelIndex labelIndex, Register predicate, bool inv_pred=false) {
- GBE_ASSERT(op == OP_BRA || op == OP_IF);
+ GBE_ASSERT(op == OP_BRA || op == OP_IF || op == OP_WHILE);
this->opcode = op;
this->predicate = predicate;
this->labelIndex = labelIndex;
@@ -1721,6 +1721,11 @@ DECL_MEM_FN(GetImageInfoInstruction, uint8_t, getImageIndex(void), getImageIndex
return internal::BranchInstruction(OP_ENDIF, labelIndex).convert();
}
+ // WHILE
+ Instruction WHILE(LabelIndex labelIndex, Register pred) {
+ return internal::BranchInstruction(OP_WHILE, labelIndex, pred).convert();
+ }
+
// RET
Instruction RET(void) {
return internal::BranchInstruction(OP_RET).convert();