diff options
| author | Luo Xionghu <xionghu.luo@intel.com> | 2015-12-10 22:22:09 -0500 |
|---|---|---|
| committer | Yang Rong <rong.r.yang@intel.com> | 2015-12-14 16:57:10 +0800 |
| commit | 9cf3952c9efe4b95690adc3a9c8ed4d08fc671ef (patch) | |
| tree | f5081199a3ebf865e79beb665379e13a808ba32f | |
| parent | b7d69e777c26a8b17e6fcecc22ff9fa4f37b1e6b (diff) | |
fix debug instruction welform assert.
handle llvm.fabs.f16 instruction in case compiler_half_isnan.
Signed-off-by: Luo Xionghu <xionghu.luo@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
| -rw-r--r-- | backend/src/llvm/llvm_gen_backend.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp index 6a3af18c..f2d3704b 100644 --- a/backend/src/llvm/llvm_gen_backend.cpp +++ b/backend/src/llvm/llvm_gen_backend.cpp @@ -4034,7 +4034,6 @@ namespace gbe break; case Intrinsic::sqrt: this->emitUnaryCallInst(I,CS,ir::OP_SQR); break; case Intrinsic::ceil: this->emitUnaryCallInst(I,CS,ir::OP_RNDU); break; - case Intrinsic::fabs: this->emitUnaryCallInst(I,CS,ir::OP_ABS); break; case Intrinsic::trunc: this->emitUnaryCallInst(I,CS,ir::OP_RNDZ); break; case Intrinsic::rint: this->emitUnaryCallInst(I,CS,ir::OP_RNDE); break; case Intrinsic::floor: this->emitUnaryCallInst(I,CS,ir::OP_RNDD); break; @@ -4052,6 +4051,13 @@ namespace gbe ctx.POW(ir::TYPE_FLOAT, dst, src0, src1); break; } + case Intrinsic::fabs: + { + const ir::Register src = this->getRegister(*AI); + const ir::Register dst = this->getRegister(&I); + ctx.ALU1(ir::OP_ABS, getType(ctx, (*AI)->getType()), dst, src); + break; + } default: NOT_IMPLEMENTED; } } else { |