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authornjn <njn@a5019735-40e9-0310-863c-91ae7b9d1cf9>2005-11-13 17:57:32 +0000
committernjn <njn@a5019735-40e9-0310-863c-91ae7b9d1cf9>2005-11-13 17:57:32 +0000
commitfcd04886dbda12c647f9e2d8dac85b2c834f0a6c (patch)
tree5c2cfa1f5434b87d512654e68313e74201c9e2e1 /cachegrind
parent99ffec4b2a139513c77a420a459d5ea9beaadb98 (diff)
Inline cachesim_*_doref(). This gains about 5--10% in speed.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5117 a5019735-40e9-0310-863c-91ae7b9d1cf9
Diffstat (limited to 'cachegrind')
-rw-r--r--cachegrind/cg_sim.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/cachegrind/cg_sim.c b/cachegrind/cg_sim.c
index 7cab553c..fe3ac934 100644
--- a/cachegrind/cg_sim.c
+++ b/cachegrind/cg_sim.c
@@ -108,7 +108,10 @@ static void cachesim_##L##_initcache(cache_t config) \
cachesim_initcache(config, &L); \
} \
\
-static /* __inline__ */ \
+/* This attribute forces GCC to inline this function, even though it's */ \
+/* bigger than its usual limit. Inlining gains around 5--10% speedup. */ \
+__attribute__((always_inline)) \
+static __inline__ \
void cachesim_##L##_doref(Addr a, UChar size, ULong* m1, ULong *m2) \
{ \
register UInt set1 = ( a >> L.line_size_bits) & (L.sets_min_1); \